參數(shù)資料
型號(hào)： M52D128168A
廠商： Elite Semiconductor Memory Technology Inc.
英文描述： 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述： 200萬(wàn)× 16位× 4個(gè)銀行同步DRAM
文件頁(yè)數(shù)： 3/47頁(yè)
文件大小： 1209K
代理商： M52D128168A
ES MT
M52D128168A
FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTION DESCRIPTION
Preliminary
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
May. 2007
3/47
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs
CS
Chip Select
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A11
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
BA0 , BA1
Bank Select Address
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
WE
Write Enable
Latches data in starting from CAS ,
WE
active.
L(U)DQM
Data Input / Output Mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15
Data Input / Output
Data inputs / outputs are multiplexed on the same pins.
VDD / VSS
Power Supply / Ground
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VDDQ / VSSQ Data Output Power / Ground
NC
No Connection
This pin is recommended to be left No Connection on the device.
L(U)DQM
DQ
Mode
Register
C
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
R
Bank A
Bank B
Sense Amplifier
Column Decoder
Data Control Circuit
L
I
B
Address
Clock
Generator
CLK
CKE
C
CS
RAS
CAS
WE
相關(guān)PDF資料
PDF描述
M52D128168A-10BG 2M x 16 Bit x 4 Banks Synchronous DRAM
M52D128168A-10TG 2M x 16 Bit x 4 Banks Synchronous DRAM
M52D128168A-7.5BG 2M x 16 Bit x 4 Banks Synchronous DRAM
M52D128168A-7.5TG 2M x 16 Bit x 4 Banks Synchronous DRAM
M52D16161A 512K x 16Bit x 2Banks Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M52D128168A_09 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Mobile Synchronous DRAM
M52D128168A_1 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM
M52D128168A-10BG 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM 128MB 1.8V 100MHZ FBGA54
M52D128168A-10BIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM
M52D128168A-10TG 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM 128MB 1.8V 100MHZ TSOPII54
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