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參數(shù)資料
| 型號： | M58BF008B100D6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit 256Kb x32, Burst Flash Memory |
| 中文描述： | 8兆位的256Kb X32號，突發(fā)快閃記憶體 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大小： | 231K |
| 代理商： | M58BF008B100D6T |
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M58BF008
Table 8. Status Register Bits
Mne-
monic
Bit
Name
Logic
Level
Definition
Note
P/ECS
7
P/E.C. Status
’1’
Ready
Indicates the P/E.C. status, check during
Program or Erase
’0’
Busy
PESS
6
Program/Erase
Suspend Status
‘1’
Suspend
On Program/Erase Suspend instruction both
P/ECS and PESS bits are set to ‘1’.
Either ES bit or PS bit is set to ‘1’.
PESS and either ES or PS bits remain at ‘1’
until Erase Resume instruction is given.
‘0’
In Progress or
Completed
ES
5
Erase Status
’1’
Erase Error or
Erase Suspend
ES bit is set to ‘1’ if either PESS instruction is
given or Erase operation fails. If ES bit is ‘1’,
check PESS bit.
’0’
Erase Success
PS
4
Program Status
’1’
Program Error or
Program Suspend
PS bit is set to ‘1’ if either PESS instruction is
given or Program operation fails.If PS bit is‘1’,
check PESS bit.
’0’
Program Success
VPPS
3
V
PP
Status
’1’
V
PP
Invalid
VPPS bit is set to ‘1’ if initially V
PP
is not V
PPH
nor V
PP1
, when Program or Erase Instruction
are executed.
’0’
V
PP
OK
Reserved
2
OBEB
1
Overlay Block
Enable Bit
’1’
Enabled
OBEB bit is set to ‘1’ when OverlayBlock is
Enabled.
’0’
Disabled
OBS
0
Overlay Block
Status
’1’
Activated
OBS bit is set to ‘1’ when OBEB is ‘1’ and V
PP
is in the range V
PP1
or V
PPH
.
’0’
Not Activated
Erase (EE).
The Erase instruction consists of two
write cycles, the first is the eraseset-up command
20h at the address 00000h. This is followed by the
Erase Confirm command D0h written to an ad-
dress within the block to be erased. If the second
is not the Erase Confirm command the Status
Register bits 4 and 5 are set to ’1’and the instruc-
tion aborts. While erasing is in progress only the
Read Status Registerand Erase Suspend instruc-
tions are valid.
Blocks are erased one at a time. An erase opera-
tion sets all bits in a block to ’1’. The erase algo-
rithm automatically programs all bits to ’0’ before
erasing the block to all ’1’s.
Read operations output the Status Register after
the erase operation has started. The Status Reg-
ister bit 7 is ’0’ while the erase is in progress andis
set to’1’ when it is completed. After completion the
Status Register bit 5 is set to ’1’if there has been
an erase failure.
Erasure should not be attempted when the V
PP
Program/Erase Supply Voltage is out of the range
V
PP1
or V
PPH
as the results will be uncertain. The
Status Register bit 3 is set to ’1’if V
PP
is not within
the allowed ranges when erasing is attempted or if
it falls out of the ranges during erase execution.
The erase operation aborts if V
PP
drops out of the
allowed range or if Reset/Power-down RP falls to
V
IL
. As data integrity cannot be guaranteed when
the erase operation is aborted, the erase must be
repeated.
A Clear Status Register instruction must be given
to clear the Status Register bits.
Overlay Block Erase (OBEE).
The
Block Erase instruction consists of two write cy-
cles, the first is the Overlay block erase set-up
command 02h at the address 00000h. This is fol-
lowed by the Overlay Block Erase Confirm com-
mand 0Dh written to an address withinthe Overlay
block. If the secondis not the Overlay Block Erase
Confirm command the Status Register bit 5 is set
to ’1’ and theinstruction aborts. While erasing is in
progress only theRead Status Register instruction
is valid.
The operation is executed as described for the
Erase (EE) instruction of the Main memory array.
A Clear Status Register instruction must be given
to clear the Status Register bits.
Overlay
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