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參數(shù)資料
| 型號(hào)： | M58BF008B100D6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit 256Kb x32, Burst Flash Memory |
| 中文描述： | 8兆位的256Kb X32號(hào)，突發(fā)快閃記憶體 |
| 文件頁(yè)數(shù)： | 5/36頁(yè) |
| 文件大?。?/td> | 231K |
| 代理商： | M58BF008B100D6T |
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M58BF008
status orsignatures read fromthe memory, or they
input data to be programmed or Instruction com-
mands to the Command Interface.
Asynchronous mode
Memory control isprovidedby Chip EnableE, Out-
put Enable G and Write Enable W for read and
write operations.
Synchronous mode
Memory control isprovided by Load BurstAddress
LBA which loads a read or write address. A Syn-
chronous Single Read or a Synchronous Burst
Read is performed under control of Output Enable
G. Synchronous Write is controlled by Write/Read
Enable WR, Load Burst Address LBA and Write
Enable W. Internaladvance of the burstaddress is
controlled by Burst Address Advance BAA.
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A17).
The address signal
A17 is the MSB and A0 the LSB.
In theAsynchronous mode theaddresses must be
stable before Chip Enable E and Write Enable W
go to V
IL
. They must remain stable during the read
or write cycle.
In the Synchronous modes, the addresses are
latched by the rising edge of the System Clock
CLK when both Latch Burst Address LBA and
Chip Enable E are at V
IL
. The addresses are
latched for a read operationif Write/Read WR is at
V
IH
or for a write operation when it is at V
IL
.
Data Input/Output (DQ0-DQ31).
The data signal
DQ31 is the MSB and DQ0 the LSB. Commands
are input on DQ0-DQ7.
Data input is a Double-Wordto be programmed in
the memory or an Instruction command to the
Command Interface. Data is read from theMain or
Overlay memory blocks, the Status Register orthe
Electronic Signature.
In the Asynchronous mode data is read when the
addresses are stable and Chip EnableE and Out-
put Enable G are at V
IL
. Commands or address/
data are written when Chip Enable Eand Write W
are at V
IL
.
In the Synchronous mode, after addresses are
latched, data is read on a rising edge of the Sys-
tem Clock CLK when Chip Enable E is at V
IL
and
if Output Enable was at V
IL
on the previous rising
clock edge. Data is written on a rising edge of the
System Clock CLK when Chip Enable E and Write
Enable W are at V
IL
.
The outputs are high impedance when Chip En-
able E or OutputEnable G are at V
IH
, or when Out-
put Disable GD is at V
IL
. Outputs are also high
impedance when System Reset RP is at V
IL
.
Table 3. Block Addresses
#
Size
(Kbit)
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
Address Range
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
3E000-3FFFF
3C000-3DFFF
3A000-3BFFF
38000-39FFF
36000-37FFF
34000-35FFF
32000-33FFF
30000-31FFF
2E000-2FFFF
2C000-2DFFF
2A000-2BFFF
28000-29FFF
26000-27FFF
24000-25FFF
22000-23FFF
20000-21FFF
1E000-1FFFF
1C000-1DFFF
1A000-1BFFF
18000-19FFF
16000-17FFF
14000-15FFF
12000-13FFF
10000-11FFF
0E000-0FFFF
0C000-0DFFF
0A000-0BFFF
08000-09FFF
06000-07FFF
04000-05FFF
02000-03FFF
00000-01FFF
00000-01FFF
Overlay Block
ORGANISATION
The M58BF008 has a data path width of 32 bit
(Double-Word) and isorganised as a Main memo-
ry array of 32 blocks of 256 Kbit plus an Overlay
block of 256 Kbit having the same address space
as the first Main memory block. The memory map
is shown in Table 3.
The memory is addressed by A0-A17 which are
static for Asynchronous or latched for Synchro-
nous operation. Data Input/Output is static or
latched on DQ0-DQ31, these signals output data,
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