參數(shù)資料
型號(hào)： M58BF008B100D6T
廠商： 意法半導(dǎo)體
英文描述： 8 Mbit 256Kb x32, Burst Flash Memory
中文描述： 8兆位的256Kb X32號(hào)，突發(fā)快閃記憶體
文件頁數(shù)： 6/36頁
文件大?。?/td> 231K
代理商： M58BF008B100D6T
M58BF008
6/36
System Clock (CLK).
All synchronous signals
are input and output relative to the System Clock.
Synchronous input signals must respect the set-
up and hold times relative to the System Clock ris-
ing edge.
Reset/Power-down (RP).
The
down RP input provides a hardware reset for the
memory. When Reset/Power-down RP is at V
IL
the memoryis reset and in thePower-down mode.
In this mode the outputs are high impedance and
the current consumption is minimised. When Re-
set/Power-down RP is at V
IH
the memory is in the
normal operating mode. When leaving the Power-
down mode the memory enters the Asynchronous
Read Array mode.
Reset/Power-down has a weak pull-up resistor to
V
DDQ
and will assume a high level if not connect-
ed.
Chip Enable (E).
When the Chip Enable E input
is atV
IL
it activates thememory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable E is at V
IH
the memory is deselected
and the power consumption is reduced to the
standby level.
Output Enable (G).
Output EnableG controls the
data output buffers. In the Asynchronous mode
data is output when Output Enable G is at V
IL
. In
the Synchronous mode, Output Enable G is sam-
pled on the rising edge of the System Clock CLK.
If Output Enable E is at V
IL
then valid output data
on DQ0-DQ31 can be read at the next rising edge
of the System Clock CLK.
Output Disable (GD).
In
mode thedata outputs DQ0-DQ31 are highimped-
ance when Output Disable GD is at V
IL
, irrespec-
tive of the state of Output
Synchronous mode Output Disable GD is sam-
pled, together with Output Enable G, on the rising
edge of the System Clock CLK. If Output Disable
is atV
IL
thenthe data outputs DQ0-DQ31 arehigh
impedance at the next rising edge of the System
Clock CLK, irrespective of the state of Output En-
able G.
Output Disable has a weak pull-up resistor to
V
DDQ
and will assume a high level if not externally
connected.
Write Enable (W).
The Write Enable W input
controls the writing of commands or input data. In
the Asynchronous mode commands or data are
written when Chip Enable E and Write Enable W
are at V
IL
. In the Synchronous mode with Chip En-
able E at V
IL
, input data is sampled if Write Enable
W is at V
IL
on the rising edgeof the System Clock
CLK.
Reset/Power-
the
Asynchronous
Enable
G. In
Load Burst Address (LBA).
In
nous mode Load Burst Address LBA is Don’t Care
(but if it falls during an asynchronous read then a
new read cycle is started). In the Synchronous
mode Load BurstAddress LBAenables latching of
the burst startingaddress for Synchronous read or
write. The address is latched on the rising edge of
the System Clock CLK if Load Burst Address LBA
is at V
IL
.
Write/Read (WR).
Write/Read WR is used in
Synchronous mode to control write or read opera-
tions. If Load Burst Address LBA is at V
IL
and
Write/Read is at V
IL
then the rising edge of the
System Clock CLK latches a write address. If
Write/Read is at V
IH
then a read address is
latched.
Write/Read has a weak pull-up resistor to V
DDQ
and will assume a high level if not externally con-
nected.
Burst Address Advance (BAA).
When
Address Advance BAA is at V
IL
, the rising edge of
the System Clock CLK advances the burst ad-
dress. WhenBurst Address Advance BAA isat V
IH
the advance is suspended.
V
DD
Supply Voltage.
The supply V
DD
provides
the power to the internal circuits of the memory.
The V
DD
supply voltage is 4.5 to 5.5V.
V
DDQ
Input/Output Supply Voltage.
The Input/
Output supply V
DDQ
provides thepower for the in-
put/outputs of the memory, independent from the
supply V
DD
. The Input/Output supply V
DDQ
may
be connected to the V
DD
supply or it can use a
separate supply of 3.0 to 3.6V.
V
PP
Program/Erase Supply Voltage.
The
gram/Erase supply V
PP
is used for programming
and erase operations. The memory normally exe-
cutes program and erase operations at the supply
V
PP1
voltage levels.
In a manufacturing environment, programming
may be speeded upby applying a higher V
PPH
lev-
el to the V
PP
Program/EraseSupply. This is not in-
tended for extended use. The V
PPH
supply may be
applied for a totalof 80 hoursmaximum and during
program and erase for a maximum of 1000 cycles.
Stressing the device beyond these limits could
damage the device.
When V
PP
Program/Erase supply is at V
SS
all
blocks are protected from programming or erase.
Leaving V
PP
floating is equivalent to connecting it
to V
SS
due to an internal pull-down circuit.
Ground (V
SS
and V
SSQ
).
The Ground V
SS
is the
reference for the internal supply voltage V
DD
. The
Ground V
SSQ
is the reference for the Input/Output
supply V
DDQ
.
the
Asynchro-
Burst
Pro-
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