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參數(shù)資料
| 型號： | M58LW064D11N1T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 3V PROM, 110 ns, PDSO56 |
| 封裝： | 14 X 20 MM, PLASTIC, TSOP-56 |
| 文件頁數(shù)： | 33/50頁 |
| 文件大?。?/td> | 280K |
| 代理商： | M58LW064D11N1T |
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M58LW064D
Table 30. Extended Query information
Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.
2. Not supported.
Address
Data (Hex)
Description
offset
x16
x8
(P)h
0031h
62h
50h
”P”
Query ASCII string - Extended Table
(P+1)h
0032h
64h
52h
”R”
(P+2)h
0033h
66h
49h
”Y”
(P+3)h
0034h
68h
31h
Major version number
(P+4)h
0035h
6Ah
31h
Minor version number
(P+5)h
0036h
6Ch
CEh
Optional Feature: (1=yes, 0=no)
bit0, Chip Erase Supported (0=no)
bit1, Suspend Erase Supported (1=yes)
bit2, Suspend Program Supported (1=yes)
bit3, Lock/Unlock Supported (1=yes)
bit4, Queue Erase Supported (0=no)
bit5, Instant Individual Block locking
bit6, Protection bits supported
bit7, Page Read supported
bit8, Synchronous Read supported
Bit 31-9 reserved for future use
(P+6)h
0037h
6Eh
00h
Synchronous Read supported (0=no)
(P+7)h
0038h
70h
00h
Optional Features
(P+8)h
0039h
72h
00h
(P+9)h
003Ah
74h
01h
Function allowed after Suspend:
Program allowed after Erase Suspend (1=yes)
Bit 7-1 reserved for future use
(P+A)h
003Bh
76h
01h (2)
Block Status Register Mask
(P+B)h
003Ch
78h
00h
Lock bit, no lock down
(P+C)h
003Dh
7Ah
33h
VDD OPTIMUM Program/Erase voltage conditions
(P+D)h
003Eh
7Ch
00h
VPP OPTIMUM Program/Erase voltage conditions
(P+E)h
003Fh
7Eh
01h
OTP protection: No. of protection register fields
(P+F)h
0040h
80h
Lock bit’s physical low address
(P+10)h
0041h
82h
00h
Lock bit’s physical high address
(P+11)h
0042h
84h
03h
n where 2n is number of factory reprogrammed bytes
(P+12)h
0043h
86h
03h
n where 2n is number of user programmable bytes
(P+13)h
0044h
88h
03h
Page Read: 2n Bytes (n = bits 0-7)
(P+14)h
0045h
8Ah
00h
Synchronous mode configuration fields
(P+15)h
0046h
8Ch
Reserved for future use
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