參數(shù)資料
型號: M58LW128B150N1F
廠商: 意法半導(dǎo)體
英文描述: 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
中文描述: 128兆位和8Mb x16或4Mb的X32號,統(tǒng)一座,突發(fā)3V電源閃存
文件頁數(shù): 13/65頁
文件大?。?/td> 932K
代理商: M58LW128B150N1F
13/65
M58LW128A, M58LW128B
is the LSB of the address bus. When WORD is
High, V
IH
, the Double-Word wide x32 Bus Width is
selected and the data is read and written to on
DQ0-DQ31; A2 is the LSB of the address bus and
A1 is don’t care.
Ready/Busy (RB).
The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the Program/Erase Controller is currently active.
When Ready/Busy is high impedance, the memo-
ry is ready for any read, program or erase opera-
tion. Ready/Busy is Low, V
OL
, during program and
erase operations. When the device is busy it will
not accept any additional Program or Erase com-
mands except Program/Erase Suspend. When the
Program/Erase Controller is idle, or suspended,
Ready Busy can float High through a pull-up resis-
tor.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Ready/Busy is not Low during a reset unless the
reset was applied when the Program/Erase Con-
troller was active; Ready/Busy can rise before Re-
set/Power-Down rises.
Program/Erase Enable (V
PP
).
The
Erase Enable input, V
PP,
is used to protect all
blocks, preventing Program and Erase operations
from affecting their data.
When Program/Erase Enable is Low, V
IL
, any pro-
gram or erase operation sent to the Command In-
terface will cause the V
PP
Status bit (bit3) in the
Status Register to be set. When Program/Erase
Enable is High, V
IH
, program and erase operations
can be performed on unprotected blocks. Pro-
gram/Erase Enable must be kept High during all
Program, Erase, Block Protect and Block Unpro-
Program/
tect operations, otherwise the operation is not
guaranteed to succeed and data may become cor-
rupt.
V
DD
Supply Voltage.
The Supply Voltage, V
DD
,
is the core power supply. All internal circuits draw
their current from the V
DD
pin, including the Pro-
gram/Erase Controller.
A 0.1
μ
F capacitor should be connected between
the Supply Voltage, V
DD
, and the Ground, V
SS
, to
decouple the current surges from the power sup-
ply. The PCB track widths must be sufficient to
carry the currents required during all operations of
the parts, see Table 16, DC Characteristics, for
maximum current supply requirements.
Input/Output Supply Voltage (V
DDQ
).
The
put/Output Supply Voltage, V
DDQ
, is the input/out-
put buffer power supply. All input and output pins
and voltage references are powered and mea-
sured relative to the Input/Output Supply Voltage
pin, V
DDQ
.
The Input/Output Supply Voltage, V
DDQ
, must al-
ways be equal or less than the V
DD
Supply Volt-
age, including during Power-Up.
A 0.1
μ
F capacitor should be connected between
the Input/Output Supply Voltage, V
DDQ
, and the
Ground, V
SSQ
, to decouple the current surges
from the power supply. If V
DDQ
and V
DD
are con-
nected together then only one decoupling capaci-
tor is required.
Ground (V
SS
).
Ground, V
SS,
is the reference for
all core power supply voltages.
Ground (V
SSQ
).
Ground, V
SSQ,
is the reference
for input/output voltage measurements. It is es-
sential to connect V
SS
and
V
SSQ
to the same
ground
.
In-
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