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參數(shù)資料
| 型號： | M58LW128B150N6E |
| 廠商： | 意法半導體 |
| 英文描述： | 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| 中文描述： | 128兆位和8Mb x16或4Mb的X32號，統(tǒng)一座，突發(fā)3V電源閃存 |
| 文件頁數(shù)： | 15/65頁 |
| 文件大小： | 932K |
| 代理商： | M58LW128B150N6E |
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15/65
M58LW128A, M58LW128B
first. The Data Inputs/Outputs are latched by the
Command Interface on the rising edge of Chip En-
able or Write Enable, whichever occurs first. Out-
put Enable must remain High, V
IH
, during the
whole Asynchronous Bus Write operation. See
Figures 16 and 18 Asynchronous Latch Controlled
Write AC Waveforms, and Tables 20 and 21,
Asynchronous Write and Latch Controlled Write
AC Characteristics, for details of the timing re-
quirements.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when the Output Enable
is High.
Standby.
When Chip Enable is High, V
IH
, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high imped-
ance state regardless of Output Enable or Write
Enable. The Supply Current is reduced to the
Standby Supply Current, I
DD1
.
During Program or Erase operations the memory
will continue to use the Program/Erase Supply
Current, I
DD3
, for Program or Erase operations un-
til the operation completes.
Power-Down.
The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
current is reduced to I
DD2
, and the outputs are
high impedance, independent of Chip Enable,
Output Enable or Write Enable.
Table 2. Asynchronous Bus Operations
Note: 1.
X = Don’t Care V
IL
or V
IH
. High = V
IH
or V
HH
.
2. M15 = 1, Bits M15 and M3 are in the Burst Configuration Register.
Bus Operation
Step
E
G
W
RP
M3
(2)
L
A1-A23
DQ0-DQ31
Asynchronous Bus Read
V
IL
V
IL
V
IH
High
0
X
Address
Data Output
Asynchronous Latch
Controlled Bus Read
Address Latch
V
IL
V
IL
V
IH
High
1
V
IL
Address
High Z
Read
V
IL
V
IL
V
IH
High
1
V
IH
X
Data Output
Asynchronous Page Read
V
IL
V
IL
V
IH
High
0
X
Address
Data Output
Asynchronous Bus Write
V
IL
V
IH
V
IL
High
X
V
IL
Address
Data Input
Asynchronous Latch
Controlled Bus Write
Address Latch
V
IL
V
IH
V
IL
High
X
V
IL
Address
Data Input
Output Disable
V
IL
V
IH
V
IH
High
X
X
X
High Z
Standby
V
IH
X
X
High
X
X
X
High Z
Power-Down
X
X
X
V
IL
X
X
X
High Z
相關PDF資料 |
PDF描述 |
|---|---|
| M58LW128B150N6F | 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW128B150N6T | 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW128B150ZA1E | 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW128B150ZA1F | 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW128B150ZA1T | 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M58LW128B150N6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW128B150N6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW128B150ZA1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW128B150ZA1F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW128B150ZA1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
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