參數(shù)資料
型號(hào): M58WR032FT80ZB6T
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
中文描述: 32兆位(含2Mb × 16,多銀行,突發(fā))1.8V電源快閃記憶體
文件頁數(shù): 68/86頁
文件大小: 1306K
代理商: M58WR032FT80ZB6T
M58WR032FT, M58WR032FB
68/86
Note: 1. The variable P is a pointer which is defined at CFI offset 15h.
2. Bank Regions. There are two Bank Regions, see
Table 28.
and
Table 29.
(P+35)h = 6Eh
03h
(P+3D)h = 76h
03h
Bank Region 2 (Erase Block Type 1): Page mode and
synchronous mode capabilities (defined in table 10)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+36)h = 6Fh
07h
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
(P+37)h = 70h
00h
(P+38)h = 71h
20h
(P+39)h = 72h
00h
(P+3A)h = 73h
64h
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
(P+3B)h = 74h
00h
(P+3C)h = 75h
01h
Bank Region 2 (Erase Block Type 2): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+3D)h = 76h
03h
Bank Region 2 (Erase Block Type 2): Page mode and
synchronous mode capabilities (defined in table 10)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+3E)h = 77h
(P+3E)h = 77h
Feature Space definitions
(P+3F)h = 78h
(P+3F)h = 78h
Reserved
M58WR032FT (top)
M58WR032FB (bottom)
Description
Offset
Data
Offset
Data
相關(guān)PDF資料
PDF描述
M58WR032FB60ZB6 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
M58WR032FB60ZB6E 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
M58WR032FB60ZB6F 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
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