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參數(shù)資料
| 型號(hào)： | M59DR032BN |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit 2Mb x16, Dual Bank, Page Low Voltage Flash Memory |
| 中文描述： | 32兆位的2Mb x16插槽，雙行，第低壓閃存 |
| 文件頁數(shù)： | 12/38頁 |
| 文件大?。?/td> | 270K |
| 代理商： | M59DR032BN |
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M59DR032A, M59DR032B
12/38
Table 14A. Instructions
(1,2)
Mne.
Instr.
Cyc.
1st Cyc.
2nd Cyc.
3rd Cyc.
4th Cyc.
5th Cyc.
6th Cyc.
RD
(4)
Read/Reset
Memory Array
1+
Addr.
(3)
X
Read Memory Array until a new write cycle is initiated.
Data
F0h
3+
Addr.
555h
2AAh
555h
Read Memory Array until a new
write cycle is initiated.
Data
AAh
55h
F0h
RCFI
CFI Query
1+
Addr.
55h
Read CFI data until a new write cycle is initiated.
Data
98h
AS
(4)
Auto Select
3+
Addr.
555h
2AAh
555h
Read electronic Signature or
Block Protection or Configuration
Register Status until a new cycle
is initiated.
Data
AAh
55h
90h
CR
Configuration
Register Write
4
Addr.
555h
2AAh
555h
Configura-
tion Data
Data
AAh
55h
60h
03h
PG
Program
4
Addr.
555h
2AAh
555h
Program
Address
Read Data Polling or
Toggle Bit until
Program completes.
Data
AAh
55h
A0h
Program
Data
DPG
Double Word
Program
5
Addr.
555h
2AAh
555h
Program
Address 1
Program
Address 2
Note 6, 7
Data
AAh
55h
40h
Program
Data 1
Program
Data 2
EBY
Enter Bypass
Mode
3
Addr.
555h
2AAh
555h
Data
AAh
55h
20h
XBY
Exit Bypass
Mode
2
Addr.
X
X
Data
90h
00h
PGBY
Program in
Bypass Mode
2
Addr.
X
Program
Address
Read Data Polling or Toggle Bit until Program
completes.
Data
A0h
Program
Data
DPGBY
Double Word
Program in
Bypass Mode
3
Addr.
X
Program
Address 1
Program
Address 2
Note 6, 7
Data
40h
Program
Data 1
Program
Data 2
BP
Block Protect
4
Addr.
555h
2AAh
555h
Block
Address
Data
AAh
55h
60h
01h
BU
Block Unprotect
1
Addr.
555h
2AAh
555h
Block
Address
Data
AAh
55h
60h
D0h
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