參數(shù)資料
型號(hào)： M5LV-128/68-10VI
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 39/42頁
文件大小： 0K
描述： IC CPLD 128MC 68I/O 100TQFP
標(biāo)準(zhǔn)包裝： 90
系列： MACH® 5
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 10.0ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
宏單元數(shù)： 128
輸入/輸出數(shù)： 68
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
6
MACH 5 Family
Macrocells
The macrocells for MACH 5 devices consist of a storage element which can be configured for combinatorial,
registered or latched operation (Figure 3). The D-type flip-flops can be configured as T-type, J-K, or S-R
operation through the use of the XOR gate associated with each macrocell.
Each PAL block has the capability to provide two input registers by using macrocells 0 and 15. In order to use
this option, these macrocells must be accessed via the I/O pins associated with macrocells 3 and 12,
respectively. Once the macrocell is used as an input register, it cannot be used for logic, so its clusters can be
re-directed through the logic allocator to another macrocell. The
I/O pins associated with macrocells 0 and 15 can still be used as input pins. Although the I/O pins for
macrocells 3 and 12 are used to connect to the input registers, these macrocells can still be used as “buried”
macrocells to drive device logic via the matrix.
Control Generator
The control generator provides four configurable clock lines and three configurable set/reset lines to each
macrocell in a PAL block. Any of the four clock lines and any of the three set/reset lines can be independently
selected by any flip-flop within a block. The clock lines can be configured to provide synchronous global (pin)
clocks and asynchronous product term clocks, sum term clocks, and latch enables (Figure 4). Three of the four
global clocks, as well as two product-term clocks and one sum-term clock, are available per PAL block. Positive
or negative edge clocking is available as well as advanced clocking features such as
complementary and
biphase clocking. Complementary clocking provides two clock lines exactly 180 degrees out of phase, and is
useful in applications such as fast data paths. A biphase clock line clocks flip-flops on both the positive and
negative edges of the clock. The configuration options for the four clock lines per PAL block are as follows:
Clock Line 0 Options
◆ Global clock (0, 1, 2, or 3) with positive or negative edge clock enable
◆ Product-term clock (A*B*C)
◆ Sum-term clock (A+B+C)
Clock Line 1 Options
◆ Global clock (0, 1, 2, or 3) with positive edge clock enable
◆ Global clock (0, 1, 2, or 3) with negative edge clock enable
Logic
Allocator
5-8
Clusters/
MC
Prog. Polarity
Mode
Selection
Control
Bus
Macrocell
D
Q
20446G-003
Figure 3. Macrocell Diagram
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料
PDF描述
VE-B4N-CY-F3 CONVERTER MOD DC/DC 18.5V 50W
EBA15DTMN CONN EDGECARD 30POS R/A .125 SLD
M5-128/68-7YC/1 IC CPLD ISP 128MC 68IO 100PQFP
VE-B4N-CY-F2 CONVERTER MOD DC/DC 18.5V 50W
MIC3775-3.3BMM IC REG LDO 3.3V .75A 8-MSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5LV-256/104-10AC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10AI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10HC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10HI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10VC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM HI DENSITY CPLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*