◆ Global clock (0, 1, 2, or 3) with positive and negative edge clock enable (biphase) C" />
參數(shù)資料
型號(hào)： M5LV-128/68-10VI
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 40/42頁(yè)
文件大?。?/td> 0K
描述： IC CPLD 128MC 68I/O 100TQFP
標(biāo)準(zhǔn)包裝： 90
系列： MACH® 5
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 10.0ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
宏單元數(shù)： 128
輸入/輸出數(shù)： 68
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
MACH 5 Family
7
◆ Global clock (0, 1, 2, or 3) with positive and negative edge clock enable (biphase)
Clock Line 2 Options
◆ Global clock (0, 1, 2, or 3) with clock enable
Clock Line 3 Options
◆ Complement of clock line 2 (same clock enable)
◆ Product-term clock (if clock line 2 does not use clock enable
The set/reset generation portion of the control generator (Figure 5) creates three set/reset lines for the PAL
block. Each macrocell can choose one of these three lines or choose no set/reset at all. All three lines can be
configured for product term set/reset and two of the three lines can be configured as sum term set/reset and
one of the lines can be configured as product-term or sum-term latch enable. While the set/reset signals are
generated in the control generator, whether that signal sets or resets a flip-flop is determined within the
individual macrocell. The same signal can set one flip-flop and reset another. PT2 or /PT2 can also be used
as a latch enable for macrocells configured as latches.
0
1
2
3
0
1
2
3
0
1
2
3
CLKIN
Clock Enable
N (0)
N (1)
OUT
MUX 2TO1
/CLK
F0
/CLK
CLK
CLKEN1
BIPHASE
CLKEN2
OUT
CLK0
CLK1
CLK2
CLK3
CLKIN
Clock Enable
MUX 2TO1
/CLK2
PTCLK
F0
Block
Clocks
0–3
PT (0:3)
PINCLK (0:3)
PT0
PT1
PT2
PT3
MUX 4TO1
IN (0)
IN (1)
IN (2)
IN (3)
OUT
U1
F0
F1
MUX 4TO1
IN (0)
IN (1)
IN (2)
IN (3)
OUT
U2
F0
F1
MUX 4TO1
IN (0)
IN (1)
IN (2)
IN (3)
OUT
U3
F0
F1
MUX
2TO1
MUX 2TO1
F0
20446G-004
Figure 4. Clock Generator
SET2/RST2/LE
Block
Sets/Reset
0–2, LE
PT (0:2)
PT0
PT1
PT2
SET1/RST1
SET0/RST0
MUX 2TO1
OUT
F0
PT1
/PT1(ST)
MUX 2TO1
OUT
F0
PT2
/PT2
20446G-005
Figure 5. Set/Reset Generator
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5LV-256/104-10AC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10AI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10HC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10HI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10VC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM HI DENSITY CPLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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