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參數(shù)資料
| 型號： | M5M5256DFP-70LLI#SM |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 70 ns, PDSO28 |
| 封裝： | 0.450 INCH, LEAD FREE, SOP-28 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 160K |
| 代理商： | M5M5256DFP-70LLI#SM |
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
FUNCTION
The operation mode of the M5M5256DFP,VP is
determined by a combination of the device control inputs
/S, /W and /OE. Each mode is summarized in the function
table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set
up before the write cycle and must be stable during the
entire cycle. The data is latched into a cell on the trailing
edge of /W, /S, whichever occurs first, requiring the set-
up and hold time relative to these edge to be maintained.
The output enable /OE directly controls the output stage.
Setting the /OE at a high level,the output stage is in a
high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
FUNCTION TABLE
Mode
DQ
Icc
/S
/W
/OE
Non selection
Write
Read
Stand-by
Active
Active
Active
High-impedance
D
IN
D
OUT
X
X
L
L
L
L
X
L
H
H
H
H
High-impedance
2
A read cycle is executed by setting /W at a high level
and /OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at
+2V power supply, enabling battery back-up operation
during power failure or power-down operation in the non-
selected mode.
VCC
(5V)
GND
(0V)
27
20
22
2
2
3
4
6
5
7
25
26
1
8
9
10
21
23
24
12
11
13
15
16
17
18
19
(512 ROWS X
512 COLUMNS)
32768 WORD
X 8BIT
GENERATOR
CLOCK
A 14
A 13
A 8
A 12
A 6
A 7
A 10
A 0
A 1
A 2
A 3
A 4
A 5
A 11
A 9
/W
/OE
/S
28
14
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
ADDRESS
INPUT
DATA I/O
WRITE CONTROL
INPUT
OUTPUT ENABLE
INPUT
CHIP SELECT
INPUT
BLOCK DIAGRAM
Note "H" and "L" in this table mean VIH and VIL, respectively.
"X" in this table should be "H" or "L".
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M5256DFP-70LLITR | 制造商:Renesas Electronics Corporation 功能描述:ASYNCH SRAM 256KB 32KX8 70NS SOP28 INDUSTRIAL TEMP - Tape and Reel |
| M5M5256DFP-70VLL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5256DFP-70VLL-I | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5256DFP-70VLL-W | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5256DFP-70VXL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
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