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參數(shù)資料
| 型號： | M7040N-066ZA1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CAP 0.01PF 50V 10% X7R AXIAL BULK P-MIL-PRF-39014 |
| 中文描述： | 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進(jìn)入搜索引擎 |
| 文件頁數(shù)： | 128/159頁 |
| 文件大?。?/td> | 1088K |
| 代理商： | M7040N-066ZA1T |
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M7040N
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SRAM ADDRESSING
Table 52 describes the commands used to gener-
ate addresses on the SRAM Address Bus. The in-
dex [15:0] field contains the address of a 72-bit
entry that results in a hit in 72-bit-configured quad-
rant. It is the address of the 72-bit entry that lies at
the 144-bit page, and the 288-bit page boundaries
in 144-bit- and 288-bit-configured quadrants, re-
spectively.
REGISTERS, page 22 of this specification, de-
scribes the NFA and SSR Registers. ADR[15:0]
contains the address supplied on the DQ Bus dur-
ing PIO access to the M7040N. Command Bits 8,
7, and 6 {CMD[8:6]} are passed from the com-
mand to the SRAM Address Bus (see COMMAND
CODES AND PARAMETERS, page 30 for more
information). ID[4:0] is the ID of the device driving
the SRAM Bus (see Figure 3, page 9 and Table 2,
page 8 for more information).
Table 52. Generating an SRAM Bus Address
SRAM PIO Access
SRAM READ enables READ access to off-chip
SRAM that contains associative data. The latency
from the issuance of the READ Instruction to the
address appearing on the SRAM Bus is the same
as the latency of the SEARCH Instruction and will
depend on the TLSZ value parameter pro-
grammed in the device Configuration Register.
The latency of the ACK from the READ Instruction
is the same as the latency of the SEARCH Instruc-
tion to the SRAM address plus the HLAT pro-
grammed in the Configuration Register.
Note:
SRAM READ is a blocking operation
–
no
new instruction can begin until the ACK is returned
by the selected device performing the access.
SRAM WRITE enables WRITE access to the off-
chip SRAM containing associative data. The laten-
cy from the second cycle of the WRITE Instruction
to the address appearing on the SRAM Bus is the
same as the latency of the SEARCH Instruction
and will depend on the TLSZ value parameter pro-
grammed in the device Configuration Register.
Note:
SRAM WRITE is a pipelined operation
–
new instruction can begin right after the previous
command has ended.
SRAM READ with a Table of One Device
SRAM READ enables READ access to the off-
chip SRAM containing associative data. The laten-
cy from the issuance of the READ Instruction to
the address appearing on the SRAM Bus is the
same as the latency of the SEARCH Instruction
and will depend on the TLSZ value parameter pro-
grammed in the device configuration register. The
latency of the ACK from the READ Instruction is
the same as the latency of the SEARCH Instruc-
tion to the SRAM address plus the HLAT pro-
grammed in the configuration register.
The following explains the SRAM READ operation
in a table with only one device that has the follow-
ing parameters: TLSZ = 00, HLAT = 000, LRAM =
1, and LDEV = 1. Figure 96, page 129 shows the
associated timing diagram.
For the following description, the selected device
refers to the only device in the table because it is
the only device to be accessed.
The sequence of the operation is as follows:
–
Cycle 1A:
The host ASIC applies the READ In-
struction on the CMD[1:0], using CMDV = 1.
The
DQ
Bus
supplies
DQ[20:19] set to '10' to select the SRAM ad-
dress. The host ASIC selects the device for
which the ID[4:0] matches the DQ[25:21] lines.
During this cycle, the host ASIC also supplies
SADR[23:21] on CMD[8:6] in this cycle.
–
Cycle 1B:
The host ASIC continues to apply the
READ Instruction
on
CMDV = 1. The DQ Bus supplies the address
with DQ[20:19] set to '10' to select the SRAM
address.
the
address
with
the
CMD[1:0]
using
Command
SRAM Operation
23
22
21
[20:16]
[15:0]
SEARCH
READ
C8
C7
C6
ID[4:0]
Index[15:0]
LEARN
WRITE
C8
C7
C6
ID[4:0]
NFA[15:0]
PIO READ
READ
C8
C7
C6
ID[4:0]
ADR[15:0]
PIO WRITE
WRITE
C8
C7
C6
ID[4:0]
ADR[15:0]
Indirect Access
WRITE/READ
C8
C7
C6
ID[4:0]
SSR[15:0]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7040N-083ZA1T | CAP 5600PF 100V 10% X7R AXIAL BULK P-MIL-PRF-39014 |
| M7040N-100ZA1T | 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| M708 | PCM REMOTE CONTROL TRANSMITTER |
| M708A | PCM REMOTE CONTROL TRANSMITTER |
| M708B1 | PCM REMOTE CONTROL TRANSMITTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7040N-083ZA1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| M7040N-100ZA1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| M7041 | 制造商:Tamura Corporation of America 功能描述: |
| M7045 | 制造商:Tamura Corporation of America 功能描述: |
| M705-5090142 | 功能描述:直流電源連接器 FEMALE STEREO JACK RoHS:否 制造商:Kycon 產(chǎn)品:Receptacles 觸點內(nèi)徑: 觸點外徑: 中心腳長度: 電流額定值:7.5 A 電壓額定值:20 V 安裝角:Right 安裝風(fēng)格:Cable |
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