參數(shù)資料
型號(hào)： M7040N-066ZA1T
廠商： 意法半導(dǎo)體
英文描述： CAP 0.01PF 50V 10% X7R AXIAL BULK P-MIL-PRF-39014
中文描述： 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進(jìn)入搜索引擎
文件頁數(shù)： 20/159頁
文件大?。?/td> 1088K
代理商： M7040N-066ZA1T
M7040N
20/159
Command Bus (CMD[10:0].
[1:0] specifies the
command; [10:2] contains the command parame-
ters. The descriptions of individual commands ex-
plains the details of the parameters. The encoding
of commands based on the [1:0] field are:
–
00: PIO READ
–
01: PIO WRITE
–
10: SEARCH
–
11: LEARN
Command Valid (
CMDV)
.
Qualifies the CMD bus
as follows:
–
0: No Command
–
1: Command
Address/Data Bus (
DQ[71:0])
.
Carries the Read
and WRITE address as well as the data during
register, data, and mask array operations. It car-
ries the compare data during search operations. It
also carries the SRAM address during SRAM PIO
accesses.
READ Acknowledge (ACK).
Indicates that valid
data is available on the DQ Bus during register,
data, and mask array READ operations, or the
data is available on the SRAM data bus during
SRAM READ operations.
Note:
ACK Signals require a weak external pull-
down resistor such as 47 or 100 K
.
End of Transfer (EOT).
Indicates
burst transfer during READ or WRITE burst oper-
ations.
Note:
EOT Signals require a weak external pull-
down resistor such as 47 K
or 100 K
.
SEARCH Successful Flag (SSF).
When assert-
ed, this signal indicates that the device is the glo-
bal winner in a SEARCH operation.
SEARCH Successful Flag Valid (SSV).
When
asserted, this signal qualifies the SSF signal.
Multiple Hit Flag (MULTI_HIT).
When asserted,
this signal indicates that there is more than one lo-
cation having a match on this device.
High Speed (HIGH_SPEED).
When this signal is
high, the device will run up to 100MHz and perform
100 million searches per second. However, in this
mode, a TLSZ value of '00' is not supported in a
system of a single device. Furthermore, the device
will only support a TLSZ of '00' and '01' if more
than one device is cascaded to form database ta-
bles.
the
end
of
Clock Tune [3:0] (CLK_TUNE[3:0]).
These test
pins should be set to logic level 1001.
SRAM Address (SADR[23:0]).
This
tains address lines to access off-chip SRAMs that
contain associative data. See Table 52, page 128
for the details of the generated SRAM address. In
a database of multiple M7040Ns, each corre-
sponding bit of SADR from all cascaded devices
must be connected.
SRAM Chip Enable (CE_L).
This is Chip Enable
control for external SRAMs. In a database of mul-
tiple M7040Ns, CE_L of all cascaded devices
must be connected. This signal is then driven by
only one of the devices.
SRAM Write Enable (WE_L).
This is Write En-
able control for external SRAMs. In a database of
multiple M7040Ns, WE_L of all cascaded devices
must be connected together. This signal is then
driven by only one of the devices.
SRAM Output Enable (OE_L).
This
Enable control for external SRAMs. Only the last
device drives this signal (with the LRAM bit set).
Address Latch Enable (ALE_L).
When this sig-
nal is low, the addresses are valid on the SRAM
Address Bus. In a database of multiple M7040Ns,
the ALE_L of all cascaded devices must be con-
nected. This signal is then driven by only one of
the devices.
Local Hit In (LHI[6:0]).
These
cade the device to form a larger table size. One
signal of this bus is connected to the LHO[1] or
LHO[0] of each of the upstream devices in a block.
Connect all unused LHI pins to a logic '0.' (For
more
information,
see
page 124.)
Local Hit Out (LHO[1:0]).
LHO[1]
are the same logical signal. LHO[1] or LHO[0] is
connected to one input of the LHI bus of up to four
downstream devices (in a block that contains up to
eight
devices).
(For
more
DEPTH-CASCADING, page 124.)
Block Hit In (BHI[2:0]).
Inputs from the previous
BHO[2:0] are tied to the BHI[2:0] of the current de-
vice (see DEPTH-CASCADING, page 124). In a
four-block system, the last block can contain only
seven devices because the ID code 11111 is used
for broadcast access.
Block Hit Out (BHO[2:0]).
These outputs from
the last device in a block are connected to the
BHI[2:0] inputs of the devices in the downstream
blocks (see DEPTH-CASCADING, page 124).
bus
con-
is
Output
pins
depth-cas-
DEPTH-CASCADING,
and
LHO[0]
information,
see
相關(guān)PDF資料
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