參數(shù)資料
型號: M7040N-066ZA1T
廠商: 意法半導體
英文描述: CAP 0.01PF 50V 10% X7R AXIAL BULK P-MIL-PRF-39014
中文描述: 64K的× 72位的網(wǎng)絡數(shù)據(jù)包進入搜索引擎
文件頁數(shù): 144/159頁
文件大?。?/td> 1088K
代理商: M7040N-066ZA1T
M7040N
144/159
SRAM WRITE with Table(s) of Up to 31 Devices
The following explains the SRAM WRITE opera-
tion done through a table(s) of up to 31 devices
with the following parameters (TLSZ = 10). The di-
agram of such table(s) is shown in Figure 107,
page 145. The following assumes that SRAM ac-
cess is done through M7040N Device 0
Device
0 is the selected device. Figure 108, page 146 and
Figure 109, page 147 show the timing diagram for
Device 0 and Device 30, respectively.
Cycle 1A:
The host ASIC applies the WRITE In-
struction on CMD[1:0] using CMDV = 1. The DQ
Bus supplies the address with DQ[20:19] set to
'10' to select the SRAM address. The host ASIC
selects the device for which the ID[4:0] matches
the DQ[25:21] lines. The host ASIC also sup-
plies SADR[23:21] on CMD[8:6] in this cycle.
Note:
CMD[2] must be set to '0' for SRAM
WRITE because Burst WRITEs into the SRAM
are not supported.
Cycle 1B:
The host ASIC continues to apply the
WRITE Instruction on CMD[1:0] using CMDV =
1. The DQ Bus supplies the address with
DQ[20:19] set to '10' to select the SRAM ad-
dress.
Note:
CMD[2] must be set to '0' for SRAM
WRITE because Burst WRITEs into the SRAM
are not supported.
Cycle 2:
The host ASIC continues to drive
DQ[71:0]. The data in this cycle is not used by
the M7040N device.
Cycle 3:
The host ASIC continues to drive
DQ[71:0]. The data in this cycle is not used by
the M7040N device.
At the end of Cycle 3, a new command can begin.
The WRITE is a pipelined operation. The WRITE
Cycle appears at the SRAM Bus, however, with
the same latency as that of a SEARCH Instruction,
as measured from the second cycle of the WRITE
command
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