參數(shù)資料
型號: M7040N-066ZA1T
廠商: 意法半導(dǎo)體
英文描述: CAP 0.01PF 50V 10% X7R AXIAL BULK P-MIL-PRF-39014
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代理商: M7040N-066ZA1T
M7040N
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SRAM READ with a Table of Up to 31 Devices
The following explains the SRAM READ operation
accomplished through a table of up to 31 devices,
using the following parameters: TLSZ = 10. The di-
agram of such a table is shown in Figure 100,
page 135.
The following assumes that SRAM access is being
accomplished through M7040N Device 0 and that
Device 0 is the selected device. Figure 101, page
136 and Figure 102, page 137 show the timing di-
agrams for Device 0 and Device 30, respectively.
Cycle 1A:
The host ASIC applies the READ In-
struction to CMD[1:0] using CMDV = 1. The DQ
Bus supplies the address, with DQ[20:19] set to
'10,' to select the SRAM address. The host
ASIC selects the device for which the ID[4:0]
matches the DQ[25:21] lines. During this cycle,
the host ASIC also supplies SADR[23:21] on
CMD[8:6].
Cycle 1B:
The host ASIC continues to apply the
READ Instruction to CMD[1:0] using CMDV = 1.
The DQ
Bus supplies
the
address, with
DQ[20:19] set to '10,' to select the SRAM ad-
dress.
Cycle 2:
The host ASIC floats DQ[71:0] to a 3-
state condition.
Cycle 3:
The host ASIC keeps DQ[71:0] in a 3-
state condition.
Cycle 4:
The selected device starts to drive
DQ[71:0].
Cycles 5 to 6:
The selected device continues to
drive DQ[71:0].
Cycle 7:
The selected device continues to drive
DQ[71:0] and drives an SRAM READ cycle.
Cycle 8:
The selected device drives ACK from
Z to low.
Cycle 9:
The selected device drives ACK to
high.
Cycle 10:
The selected device drives ACK from
high to low.
At the end of Cycle 10, the selected device floats
ACK in a 3-state condition.
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