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參數(shù)資料
| 型號： | M7A3P400-FGG484 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 400000 GATES, 350 MHz, PBGA484 |
| 封裝： | 1 MM PITCH, GREEN, FBGA-484 |
| 文件頁數(shù)： | 135/246頁 |
| 文件大小： | 3010K |
| 代理商： | M7A3P400-FGG484 |
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ProASIC3/E Flash Family FPGAs
2- 10
v2.1
Clock Resources (VersaNets)
ProASIC3 devices offer powerful and flexible control of
circuit timing through the use of analog circuitry. Each
chip has up to six CCCs. The west CCC also contains a
phase-locked loop (PLL) core, delay lines, a phase shifter
(0°, 90°, 180°, 270°), and clock multipliers/dividers. Each
CCC has all the circuitry needed for the selection and
interconnection of inputs to the VersaNet global
network. The east and west CCCs each have access to
three VersaNet global lines on each side of the chip (six
total lines). The CCCs at the four corners each have access
to three quadrant global lines in each quadrant of the
chip (except A3P030).
Advantages of the VersaNet Approach
One of the architectural benefits of ProASIC3 is the set of
powerful
and
low-delay
VersaNet
global
networks.
ProASIC3 offers six chip (main) global networks that are
distributed from the center of the FPGA array (Figure 2-9).
In addition, ProASIC3 devices have three regional globals in
each of the four chip quadrants. Each core VersaTile has
access to nine global network resources: three quadrant
and six chip (main) global networks, and a total of 18
globals on the device. Each of these networks contains
spines and ribs that reach all the VersaTiles in the quadrants
(Figure 2-10 on page 2-12). This flexible VersaNet global
network architecture allows users to map up to 144
different internal/external clocks in a ProASIC3 device.
Details on the VersaNet networks are given in Table 2-2 on
page 2-12. The flexible use of the ProASIC3 VersaNet global
network allows the designer to address several design
requirements. User applications that are clock-resource-
intensive can easily route external or gated internal clocks
using VersaNet global routing networks. Designers can also
drastically reduce delay penalties and minimize resource
usage by mapping critical, high-fanout nets to the VersaNet
global network.
In A3P030 devices, all six VersaNets are driven from three
southern I/Os, located toward the east and west sides.
These tiles can be configured to select a central I/O on
the respective side or an internal routed signal as the
input signal. The A3P030 does not support any clock
conditioning circuitry, nor does it contain the VersaNet
global network concept of top and bottom spines.
VersaNet Global Networks and Spine Access
The ProASIC3 architecture contains a total of 18
segmented
global
networks
that
can
access
the
VersaTiles, SRAM, and I/O tiles of the ProASIC3 device.
There are nine global network resources in each device
quadrant: three quadrant globals and six chip (main)
global networks. Each device has a total of 18 globals.
These VersaNet global networks offer fast, low-skew
routing resources for high-fanout nets, including clock
signals. In addition, these highly segmented global
networks offer users the flexibility to create low-skew
local
networks
using
spines
for
up
to
144internal/external clocks (in an A3P1000 device) or
other high-fanout nets in ProASIC3 devices. Optimal
usage of these low-skew networks can result in
significant improvement in design performance on
ProASIC3 devices.
The nine spines available in a vertical column reside in
global networks with two separate regions of scope: the
quadrant global network, which has three spines, and
the chip (main) global network, which has six spines.
Note that there are three quadrant spines in each
quadrant of the device (except for A3P030). There are
four quadrant global network regions per device
The spines are the vertical branches of the global
network tree, shown in Figure 2-11 on page 2-13. Each
spine in a vertical column of a chip (main) global
network is further divided into two equal-length spine
segments: one in the top and one in the bottom half of
the die.
Each spine and its associated ribs cover a certain area of
the ProASIC3 device (the "scope" of the spine; see
Figure 2-9 on page 2-11). Each spine is accessed by the
dedicated global network MUX tree architecture, which
defines how a particular spine is driven—either by the
signal on the global network from a CCC, for example, or
by another net defined by the user (Figure 2-12 on page
2-14). Quadrant spines can be driven from user I/Os on
the north and south sides of the die. The ability to drive
spines in the quadrant global networks can have a
significant effect on system performance for high-fanout
inputs to a design.
Details of the chip (main) global network spine-selection
MUX are presented in Figure 2-12 on page 2-14. The
spine drivers for each spine are located in the middle of
the die.
Quadrant spines are driven from a north or south rib.
Access to the top and bottom ribs is from the corner CCC
or from the I/Os on the north and south sides of the
device.
For details on using spines in ProASIC3 devices, see the
Actel application note Using Global Resources in Actel
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
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