參數(shù)資料
型號： MAC7121MAG40
廠商： Freescale Semiconductor
文件頁數(shù)： 47/56頁
文件大小： 0K
描述： IC MCU 32BIT FLASH 112-LQFP
標準包裝： 60
系列： MAC7xxx
核心處理器： ARM7
芯體尺寸： 32-位
速度： 40MHz
連通性： CAN，I²C，SCI，SPI
外圍設(shè)備： DMA，POR
輸入/輸出數(shù)： 85
程序存儲器容量： 544KB（544K x 8）
程序存儲器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.35 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x8/10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 112-LQFP
包裝： 托盤
MechanicalInformation
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
51
Revision History
Revision History
Version No.
Release Date
Description of Changes
Page
Numbers
v0.1
29-Oct-03
First public customer release (preliminary).
v1.0
14-Sep-04
General
Converted to Freescale identity, with blue cross-reference highlights for enhanced PDF
navigation, and miscellaneous updates for presentation consistency.
The order of Section 3.5 and Section 3.6 were reversed for better content flow. This has
caused specification numbering to change as detailed below.
Note: Content consolidation and reorganization has resulted in the following table and
specification number changes (the first spec number of each table is shown):
Added Table 1, mask set information
Updated Table 2 with expanded port pin counts, MAC71x2 and MAC71x6 family members
Pin assignment changes for mask set L47W devices:
—In Table 37, PB10 / PCS5_B / PCSS_B changed to pin 57, footnote for L49P
Table Title
Rev. 1.0
Rev. 0.1
5.0 V I/O Characteristics
Table 8
D1a Table 15 F1
3.3 V I/O Characteristics
Table 9
E1a Table 16 G1
Section 3.6, “Power Dissipation and Thermal Characteristics”
Table 10 to
Table 14
Table 7 to
Table 11
MAC71x1/6 Device Supply Current Characteristics – 40 MHz
Table 15 F1
Table 12 D1a
MAC71x1/6 Device Supply Current Characteristics – 50 MHz
Table 16 G1
N/A
VREG Operating Conditions
Table 17 H1
Table 13 E1
VREG Recommended Load Capacitances
Table 18
Table 14
Oscillator Characteristics
Table 19 J1a
Table 17 H1a
PLL Characteristics
Table 20 K1
Table 18 J1
Crystal Monitor Time-Outs
Table 21
Table 19
CRG Maximum Clock Quality Check Timings
Table 22
Table 20
CRG Startup Characteristics
Table 23 L1
Table 21 K1
External Bus Input Timing Specifications
Table 24 M1
Table 22 L1
External Bus Output Timing Specifications
Table 25 M6a Table 23 L6a
ATD Operating Characteristics in 5.0 V Range
Table 26 N1
Table 24 M1
ATD Operating Characteristics in 3.3 V Range
Table 27 P1
Table 25 N1
ATD Electrical Characteristics
Table 28 Q1
Table 26 P1
ATD Conversion Performance in 5.0 V Range
Table 29 R1
Table 27 Q1
ATD Conversion Performance in 3.3 V Range
Table 30 S1
Table 28 R1
ATD Electrical Characteristics (Operating)
N/A
Table 29 S1
ATD Performance Specifications
N/A
Table 30 T1
ATD Timing Specifications
N/A
Table 31 U1
ATD External Trigger Timing Specifications
Table 31 T1
Table 32 V1
SPI Master Mode Timing Characteristics
Table 32 U1a Table 33 W1a
SPI Slave Mode Timing Characteristics
Table 33 V1a Table 34 X1a
FlexCAN Wake-up Pulse Characteristics
Table 34 W1
Table 35 Y1
CFM Timing Characteristics
Table 35 X1
Table 36 Z1
NVM Reliability Characteristics
Table 36 X9b Table 37 Z10
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