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參數(shù)資料
型號(hào): MAC7121MAG40
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 9/56頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT FLASH 112-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: MAC7xxx
核心處理器: ARM7
芯體尺寸: 32-位
速度: 40MHz
連通性: CAN,I²C,SCI,SPI
外圍設(shè)備: DMA,POR
輸入/輸出數(shù): 85
程序存儲(chǔ)器容量: 544KB(544K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 2.35 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x8/10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 112-LQFP
包裝: 托盤
ElectricalCharacteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
17
The capacitance CP should be chosen in the range of:
Eqn. 14
The stabilization delays shown in Table 20 are dependant on PLL operational settings and external
component selection (for example, the crystal and XFC filter).
3.8.2.1
Jitter Information
With each transition of the clock fCMP, the deviation from the reference clock fREF is measured and input
voltage to the VCO is adjusted accordingly. The adjustment is done continuously with no abrupt changes
in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the
control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as
illustrated in Figure 4. It is important to note that the pre-scaler used by timers and serial modules will
eliminate the effect of PLL jitter to a large extent.
Figure 4. Jitter Definitions
The relative deviation of tNOM is at its maximum for one clock period, and decreases towards zero for
larger number of clock periods (N). Thus, jitter is defined as:
Eqn. 15
For N
< 100, the following equation is a good fit for the maximum jitter:
Eqn. 16
Figure 5. Maximum Bus Clock Jitter Approximation
C
S
20
÷
C
P
C
S
10
÷
≤≤
0
tMIN1
12
3
N–1
N
tNOM
tMAX1
tMIN(N)
tMAX(N)
JN
()
max 1
t
MAX N
()
Nt
NOM
--------------------
–1
t
MIN N
()
Nt
NOM
--------------------
,
=
JN
()
j
1
N
--------
j
2
+
=
01
5
10
20
15
N
J(N)
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