參數(shù)資料
型號(hào): MAC7121MAG40
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 49/56頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT FLASH 112-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: MAC7xxx
核心處理器: ARM7
芯體尺寸: 32-位
速度: 40MHz
連通性: CAN,I²C,SCI,SPI
外圍設(shè)備: DMA,POR
輸入/輸出數(shù): 85
程序存儲(chǔ)器容量: 544KB(544K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 2.35 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x8/10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 112-LQFP
包裝: 托盤
MechanicalInformation
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
53
v1.0
14-Sep-04
(continued)
— Rev. 0.1 redundant and superfluous content deleted
– Section 3.10.3, “ATD Electrical Specifications,” (included Table 29 and Table 30)
– Table 31, “ATD Performance Specifications” (redundant with v0.1 Table 27 and
Table 28, now Table 29 and Table 30)
Table 26 updates
– Deleted previous spec M6
– Changed spec N7 and N8 values
Table 27 updates
– Deleted previous spec N6
– Changed spec P7 and P8 values
– Changed spec P2 and footnote (1) to specify 3.15 V
Table 28 updates
– Changed spec Q2 parameter classification from T to C and 10 pF and 22 pF values
moved from maximum to typical
Table 29 updates
– Operating conditions VDDA minimum changed to 4.5 V
–VREF description moved from “conditions” header to new footnote (1)
Table 30 updates
– Operating conditions VDDA minimum changed to 3.15 V
–VREF description moved from “conditions” header to new footnote (1)
Table 31 updates
– Spec T1 description clarified, max removed, min added with footnote
– Spec T2 modified to show both edge- and level-sensitive modes
Figure 10 modified to remove “Max Frequency” label and clearly separate edge- and
level-sensitive mode timing examples
Table 32 updates
– Changed specs U1a, U1b and U4 to use fIPS and tIPS for clarity and consistency with
MAC7100RM
– Changed U1a max to and U1b min to 2 to account for the DBR bit
Table 33 updates
– Changed specs V1a, V1b, V2, V3, V4, V7, V8 to use fIPS and tIPS for clarity and
consistency with MAC7100RM
– Changed V1a max to and V1b min to 2 to account for the DBR bit
— Significant rework to match MAC7100RM clock naming, references and timing
calculations for clarity and consistency
— Changed X1 maximum from 40 MHz to 50 MHz (Table 35)
Revision History (continued)
Version No.
Release Date
Description of Changes
Page
Numbers
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