參數(shù)資料
型號： MACH131SP-7YC
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： High-Performance EE CMOS Programmable Logic
中文描述： EE PLD, 7.5 ns, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 26/47頁
文件大?。?/td> 1200K
代理商： MACH131SP-7YC
32
MACH 1 & 2 Families
Notes:
1. See “Switching Test Circuit” in the General Information section of the Vantis 1999 Data Book.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where
this parameter may be affected.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
CAPACITANCE 1
Note:
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modied where
these parameters may be affected.
tWIGL
Input Latch Gate Width LOW
234666
7.5
ns
tPDLL
Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches
11
12.5
16
17
19
23
ns
tAR
Asynchronous Reset to Registered or Latched
Output
9
9.5
13
16
19.5
20
24
ns
tARW
Asynchronous Reset Width (Note 2)
4
5
10
12
14.5
15
18
ns
tARR
Asynchronous Reset Recovery Time
(Note 2)
4
5
7.5
8
101012
ns
tAP
Asynchronous Preset to Registered or Latched
Output
9
9.5
13
16
19.5
20
24
ns
tAPW
Asynchronous Preset Width (Note 2)
4
5
10
12
14.5
15
18
ns
tAPR
Asynchronous Preset Recovery Time (Note 2)
4
5
7.5
8
10
12
ns
tEA
Input, I/O, or Feedback to Output Enable
9
9.5
10
12
15
18
ns
tER
Input, I/O, or Feedback to Output Disable
9
9.5
10
12
15
18
ns
tLP
tPD Increase for Powered-down Macrocell (Note 3)
9
10
ns
tLPS
tS Increase for Powered-down Macrocell (Note 3)
6777777
ns
tLPCO
tCO Increase for Powered-down Macrocell (Note 3)
0000000
ns
tLPEA
tEA Increase for Powered-down Macrocell (Note 3)
9
10
ns
Parameter Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0V
VCC = 5.0V,
TA = 25°C
f = 1 MHz
6pF
COUT
Output Capacitance
VOUT = 2.0V
8
pF
MACH231 AND MACH231SP (CONTINUED)
SWITCHING CHARACTERISTICS OVER OPERATING RANGES1
Parameter
Symbol
Parameter Description
-6
-7
-10
-12
-14
-15
-18
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
MACH1 High-Performance EE CMOS Programmable Logic
MACH210A-10JC High-Density EE CMOS Programmable Logic
MACH210A-10VC High-Density EE CMOS Programmable Logic
MACH210A-12JC High-Density EE CMOS Programmable Logic
MACH210A-12VC High-Density EE CMOS Programmable Logic
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MACH131SP-7YI 功能描述:CPLD - 復雜可編程邏輯器件 HI PERF EE CMOS PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
MACH210 制造商:未知廠家 制造商全稱:未知廠家 功能描述:44 pin QFP socket/28 pin DIP 0.6” plug
MACH210-12 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic
MACH21012JC 制造商:AMD 功能描述:*
MACH210-12JC 制造商:Advanced Micro Devices 功能描述:COMPLEX-EEPLD, 64-CELL, 12NS PROP DELAY, 44 Pin, Plastic, PLCC
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