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參數(shù)資料
| 型號： | MACH131SP-7YC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 7.5 ns, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 4/47頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | MACH131SP-7YC |
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12
MACH 1 & 2 Families
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in
both raw speed, and even more importantly, guaranteed xed speed. The design of the switch
matrix and PAL blocks guarantee a xed pin-to-pin delay that is independent of the logic required
by the design. Other non-Lattice/Vantis CPLDs incur serious timing delays as product terms expand
beyond their typical 4 or 5 product term limits (Figure 8). Speed and SpeedLocking combine to
give designers easy access to the performance required in today’s designs.
VCC
01
11
10
00
Output Enable
Product Terms
(Common to bank of
I/O Cells)
From Output
Macrocell
To Switch
Matrix
To Buried
Macrocell
(MACH 2 only)
Figure 7. I/O Cell
14051K-007
SpeedLocking
Shared Expander Delay
Non-MACH
5 PT
10 PT
15 PT
tPD (ns)
7.4 ns
10.4 ns
MACH 1 & 2
8.8 ns
6.6 ns
5 ns
11
10
9
8
7
6
5
5.8 ns
Product Terms
Parallel Expander Delay
Patented Architecture
Path Independent
Logic/Routing Independent
Guaranteed Fixed Timing
Up to 16 Product Terms per Output
Variable
Path Dependent
Logic/Routing Dependent Delays
Unpredictable
4-5 Product Terms before Delays
Non-MACH
MACH 1 & 2 SpeedLocking
Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices
14051K-001
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MACH1 | High-Performance EE CMOS Programmable Logic |
| MACH210A-10JC | High-Density EE CMOS Programmable Logic |
| MACH210A-10VC | High-Density EE CMOS Programmable Logic |
| MACH210A-12JC | High-Density EE CMOS Programmable Logic |
| MACH210A-12VC | High-Density EE CMOS Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MACH131SP-7YI | 功能描述:CPLD - 復雜可編程邏輯器件 HI PERF EE CMOS PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| MACH210 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:44 pin QFP socket/28 pin DIP 0.6” plug |
| MACH210-12 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH21012JC | 制造商:AMD 功能描述:* |
| MACH210-12JC | 制造商:Advanced Micro Devices 功能描述:COMPLEX-EEPLD, 64-CELL, 12NS PROP DELAY, 44 Pin, Plastic, PLCC |
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