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參數(shù)資料
| 型號(hào)： | MACH131SP-7YC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 7.5 ns, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 3/47頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | MACH131SP-7YC |
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MACH 1 & 2 Families
11
The ip-ops in either macrocell type can be clocked by one of several clock pins (Table 10).
Registers are clocked on the rising edge of the clock input. Latches hold their data when the gate
input is HIGH. Clock pins are also available as inputs, although care must be taken when a signal
acts as both clock and input to the same device.
All ip-ops have asynchronous reset and preset. This is controlled by the common product terms
that control all ip-ops within a PAL block. For a single PAL block, all ip-ops, whether in an
output or a buried macrocell, are initialized together. The initialization functionality of the ip-ops
is illustrated in Table 11.
I/O Cells
The I/O cells (Figure 7) provide a three-state output buffer. The three-state buffer can be left
permanently enabled for use only as an output, permanently disabled for use as an input, or it can
be controlled by one of two product terms for bi-directional signals and bus connections. The two
product terms provided are common to a bank of I/O cells.
Table 10. Macrocell Clocks
Device
Number of Clocks Available
Device
Number of Clocks Available
MACH111
4
MACH211SP
2
MACH111SP
2
MACH221
4
MACH131
4
MACH221SP
4
MACH131SP
4
MACH231
4
MACH211
4
MACH231SP
4
Table 11. Asynchronous Reset/Preset Operation
Conguration
AR
AP
CLK/LE
Q+
Register
0
X
See Table 9
01
X
1
10
X
0
11
X
0
Latch
0
X
See Table 9
0
1
0
Illegal
01
1
0
Illegal
10
1
0
1
0
Illegal
11
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MACH1 | High-Performance EE CMOS Programmable Logic |
| MACH210A-10JC | High-Density EE CMOS Programmable Logic |
| MACH210A-10VC | High-Density EE CMOS Programmable Logic |
| MACH210A-12JC | High-Density EE CMOS Programmable Logic |
| MACH210A-12VC | High-Density EE CMOS Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MACH131SP-7YI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 HI PERF EE CMOS PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| MACH210 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:44 pin QFP socket/28 pin DIP 0.6” plug |
| MACH210-12 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH21012JC | 制造商:AMD 功能描述:* |
| MACH210-12JC | 制造商:Advanced Micro Devices 功能描述:COMPLEX-EEPLD, 64-CELL, 12NS PROP DELAY, 44 Pin, Plastic, PLCC |
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