參數(shù)資料
型號(hào): MAQ28151CXXXX
廠(chǎng)商: DYNEX SEMICONDUCTOR LTD
元件分類(lèi): 微控制器/微處理器
英文描述: 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, CDIP28
封裝: CERAMIC, DIP-28
文件頁(yè)數(shù): 21/22頁(yè)
文件大?。?/td> 220K
代理商: MAQ28151CXXXX
MA28151
8/22
Parity error and overrun error are both checked in the same
way as in the Asynchronous Receive mode. Parity is checked
when not in HUNT, regardless of whether the Receiver is
enabled or not.
The CPU can command the receiver to enter the HUNT
mode if synchronisation is lost. This will also set all the used
character bits in the buffer to a one thus preventing a possible
false SYNDET caused by data that happens to be in the Rx
buffer at ENTER HUNT time.
Note: the SYNDET flip-flop is reset at each Status Read,
regardless of whether internal or external SYNC has been
programmed. This does not cause the MA28151 to return to
the HUNT mode. When in SYNC mode, but not in HUNT, Sync
Detection is still functional, but only occurs at the known word
boundaries. Thus, if one Status Read indicates SYNDET and a
second Status Read also indicates SYNDET, then the
programmed SYNDET characters have been received since
the previous Status Read. (If double character sync has been
contiguously received to gate a SYNDET indication). When
external SYNDET mode is selected, internal Sync Detect is
disabled, and the SYNDET flip-flop may be set at any bit
boundary.
3.9 DATA FORMAT, SYNCHRONOUS MODE
DATA CHARACTERS
ASSEMBLED SERIAL DATA OUTPUT (TxD)
SYNC CHAR 1
SYNC CHAR 2
DATA CHARACTERS
Figure 9: Receive Format, Synchronous Mode
Figure 10: Data Format, Synchronous Mode
DATA CHARACTERS
CPU BYTES (5-8 BITS/CHARACTER)
SYNC CHAR 1
SYNC CHAR 2
DATA CHARACTERS
3.8 MODE INSTRUCTION FORMAT, SYNCHRONOUS MODE
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SS ES EP PEN L2 L10
0
CHARACTER LENGTH
5
BITS
6
BITS
7
BITS
8
BITS
00
1
01
0
1
PARITY ENABLE AND SENSE
1 = ENABLE 0 = DISABLE
1 = EVEN 0 = ODD
EXTERNAL SYNC DETECT
1 = SYNCDET IS AN INPUT
0 = SYNCDET IS AN OUTPUT
SINGLE CHARACTER SYNC
1 = SINGLE SYNC CHAR.
0 = DOUBLE SYNC CHAR.
Figure 11: Mode Instruction Format, Synchronous Mode
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