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| 型號(hào)： | MAQ28151CXXXX |
| 廠商： | DYNEX SEMICONDUCTOR LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁(yè)數(shù)： | 7/22頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | MAQ28151CXXXX |
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MA28151
15/22
5. AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Condition
tCY
Internal clock cycle time
200
1000
nS
Notes 1, 5, 6
t0
External Clock high pulse width
25
-
nS
-
t0
External Clock low pulse width
25
-
nS
-
tR, tF
Clock rise and fall time
-
10
nS
-
tDTX
TxD delay from falling edge of TxD
-
1
S-
tTPW
Transmitter input clock pulse width
12xtCY
-
1 x baud rate
1xtCY
-
16 x and 64 x baud rate
tTPD
Transmitter input clock pulse delay
15xtCY
-
1 x baud rate
3xtCY
-
16 x and 64 x baud rate
tRPW
Receive input clock pulse width
12xtCY
-
1 x baud rate
1xtCY
-
16 x and 64 x baud rate
tRPD
Receive input clock pulse delay
15xtCY
-
1 x baud rate
3xtCY
-
16 x and 64 x baud rate
tTxRDY
TxRDY pin delay from CENTER of last bit
-
8xtCY
-
Note 7
tTxRDY CLEAR
TxRDY fall from falling DSN (WRITE)
-
45
-
Note 7
tRxRDY
RxRDY pin delay from center of last bit
-
26xtCY
-
Note 7
tRxRDY CLEAR
RxRDY fall from falling DSN (READ)
-
45
-
Note 7
tTxEMPTY
TxEMPTY from centre of last bit
20xtCY
-
Note 7
tWC
Control delay from rising edge of WRITE
8xtCY
-
Note 7
tCR
Control to READ set-up time (
DSR, CTS)
20xtCY
-
Note 7
tAR
Address stable before DSN (CSN, CDN)
0
-
ns
Note 2
tRA
Address hold time before DSN (CSN, CDN)
0
-
ns
Note 2
tRR
DSN pulse width
20
-
ns
-
tRD
Data delay from DSN falling (READ)
-
30
ns
Note 3
tDF
DSN rising to data floating (READ)
10
45
ns
Note 8
tDW
Data set-up time to DSN rising (WRITE)
15
-
ns
-
tWD
Data hold time to DSN rising (WRITE)
5
-
ns
-
tRV
Recovery time between writes (not shown)
6xtCY
-
Note 4
Notes: 1. AC Timings measured VOH = 1.5 VOL = 1.5.
2. CSN and Command/Data are considered as addresses.
3. Assumes that address is valid before DSN goes low.
4. This recovery time is for Mode Initialisation only. Write data is allowed when TxRDY = 1. Recovery time between
writes for Asynchronous Mode is 8xtCY and for Synchronous Mode is 16xtCY.
5. The
TxC and RxC frequencies have the following limitation with respect to clock: For 1 x baudrate, fTX or fRX≤1/
(30tCY): For 16 x and 64 x baud rate, fTX or fRX ≤1/(4.5tCY).
6. Reset Pulse Width = 6tCY minimum; System clock must be running during Reset.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
8. Data Bus connected to VDD via loads of 680 (minimum).
Mil-Std-883, method 5005, subgroups 9, 10, 11
Figure 23: AC Electrical Characteristics
Symbol
Parameter
Min.
Max.
Units
Condition
-
Clock Frequency (osc)
-
20
MHz
-
fTx
Transmitter input clock frequency
DC
64
kHz
1 x baud rate
DC
310
kHz
16 x baud rate
DC
615
kHz
64 x baud rate
fRx
Receiver input clock frequency
DC
64
kHz
1x baud rate
DC
310
kHz
16 x baud rate
DC
615
kHz
64 x baud rate
Mil-Std-883, method 5005, subgroups 7, 8A, 8B
Figure 24: Operating AC Electrical Characteristics
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