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參數(shù)資料
| 型號： | MAX1221BETX+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 14/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/DAC 12BIT W/FIFO 36TQFNEP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 50 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 225k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 2.7 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 36-TQFN 裸露焊盤（6x6） |
| 包裝： | 管件 |
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MAX1221/MAX1223/MAX1343
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________
21
the setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
sets the differential input range from 0 to VREF1. A nega-
tive differential analog input in unipolar mode causes the
digital output code to be zero. Selecting bipolar mode
sets the differential input range to ±VREF1 / 2. The digital
output code is binary in unipolar mode and two’s com-
plement in bipolar mode.
In single-ended mode, the MAX1221/MAX1223/
MAX1343 always operate in unipolar mode. The analog
inputs are internally referenced to AGND with a full-scale
input range from 0 to the selected reference voltage.
Analog Input (T/H)
The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1223. In track mode, a positive
input capacitor is connected to AIN0–AIN11 in single-
ended mode and AIN0, AIN2, AIN4–AIN10 in differential
mode. A negative input capacitor is connected to AGND
in single-ended mode or AIN1, AIN3, AIN5–AIN11 in dif-
ferential mode. The MAX1221/MAX1343 feature eight
analog input channels (AIN0–AIN7). In track mode, a pos-
itive input capacitor is connected to AIN0–AIN7 in single-
ended mode and to AIN0, AIN2, AIN4, and AIN6 in
differential mode. A negative input capacitor is connected
to AGND in single-ended mode or to AIN1, AIN3, AIN5,
and AIN7 in differential mode. For external T/H timing, use
clock mode 01. After the T/H enters hold mode, the differ-
ence between the sampled positive and negative input
voltages is converted. The input capacitance charging
rate determines the time required for the T/H to acquire
an input signal. If the input signal’s source impedance is
high, the required acquisition time lengthens.
Any source impedance below 300Ω does not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by
lengthening tACQ (only in clock mode 01) or by placing
a 1F capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-sig-
nal bandwidth, making it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequency
signals aliasing into the frequency band of interest.
Analog Input Protection
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AVDD and AGND, allowing
the inputs to swing from (AGND - 0.3V) to (AVDD +
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AVDD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
Internal FIFO
The MAX1221/MAX1223/MAX1343 contain a first-
in/first-out (FIFO) buffer that holds up to 16 ADC results
plus one temperature result. The internal FIFO allows
the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros. After each falling edge of
CS, the oldest
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
The first 2 bytes of data read out after a temperature
measurement always contain the 12-bit temperature
result, preceded by four leading zeros, MSB first. If anoth-
er temperature measurement is performed before the first
temperature result is read out, the old measurement is
overwritten by the new result. Temperature results are in
degrees Celsius (two’s complement), at a resolution of 8
AIN0–AIN11
(SINGLE-ENDED),
AIN0, AIN2,
AIN4–AIN10
(DIFFERENTIAL)
COMPARATOR
HOLD
ACQ
HOLD
ACQ
HOLD
AVDD / 2
REF1
AGND
CIN+
CIN-
DAC
AGND
(SINGLE-ENDED),
AIN1, AIN3,
AIN5–AIN11
(DIFFERENTIAL)
Figure 2. MAX1223 Equivalent Input Circuit
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1221BETX+ | 功能描述:ADC / DAC多通道 12-Bit 8Ch 300ksps 5.25V Precision ADC RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX1221BETX+T | 功能描述:ADC / DAC多通道 12-Bit 8Ch 300ksps 5.25V Precision ADC RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX1221BETX-T | 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX1223BETX | 制造商:Maxim Integrated Products 功能描述:12-BIT MULTICHANNEL ADC/DAC WITH F - Rail/Tube |
| MAX1223BETX+ | 制造商:Maxim Integrated Products 功能描述:12-BIT, MULTICHANNEL ADCS/DACS WITH FIFO, TEMPERATURE SENSIN - Rail/Tube 制造商:Maxim Integrated Products 功能描述:IC ADC 12BIT QFN 制造商:Maxim Integrated Products 功能描述:ADC / DAC Multichannel |
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