參數(shù)資料
型號： MAX19705ETM+
廠商： Maxim Integrated Products
文件頁數(shù)： 19/37頁
文件大?。?/td> 0K
描述： IC ANLG FRNT END 48-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 43
位數(shù)： 10
通道數(shù)： 4
功率（瓦特）： 28.2mW
電壓 - 電源，模擬： 2.7 V ~ 3.3 V
電壓 - 電源，數(shù)字： 1.8 V ~ 3.3 V
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-TQFN-EP（7x7）
包裝： 管件
MAX19705
10-Bit, 7.5Msps, Ultra-Low-Power
Analog Front-End
26
______________________________________________________________________________________
Mode-Recovery Timing
Figure 7 shows the mode-recovery timing diagram.
tWAKE is the wakeup time when exiting shutdown, idle,
or standby mode and entering Rx or Tx mode. tENABLE
is the recovery time when switching between either Rx
or Tx mode. tWAKE or tENABLE is the time for the Rx ADC
to settle within 1dB of specified SINAD performance and
Tx DAC settling to 10 LSB error. tWAKE and tENABLE
times are measured after either the 16-bit serial com-
mand is latched into the MAX19705 by a CS transition
high (SPI controlled) or a T/R logic transition (external
Tx-Rx control). In FAST mode, the recovery time is 0.5s
to switch between Tx or Rx modes.
System Clock Input (CLK)
Both the Rx ADC and Tx DAC share the CLK input. The
CLK input accepts a CMOS-compatible signal level set
by OVDD from 1.8V to VDD. Since the interstage con-
version of the device depends on the repeatability of
the rising and falling edges of the external clock, use a
clock with low jitter and fast rise and fall times (< 2ns).
Specifically, sampling occurs on the rising edge of the
clock signal, requiring this edge to provide the lowest
possible jitter. Any significant clock jitter limits the SNR
performance of the on-chip Rx ADC as follows:
where fIN represents the analog input frequency and
tAJ is the time of the clock jitter.
Clock jitter is especially critical for undersampling
applications. Consider the clock input as an analog
input and route away from any analog input or other
digital signal lines. The MAX19705 clock input operates
with an OVDD / 2 voltage threshold and accepts a 50%
±15% duty cycle.
log
SNR
ft
=×
××
×
20
1
2
π
IN
AJ
Figure 7. Mode-Recovery Timing Diagram
SCLK
CS
DIN
D0-D9
ID/QD
T/R
Rx - > Tx
ADC DIGITAL OUTPUT.
SINAD SETTLES WITHIN 1dB
DAC ANALOG OUTPUT
.OUTPUT SETTLES TO 10 LSB ERROR
16-BIT SERIAL DATA INPUT
tENABLE, RX EXTERNAL T/R CONTROL
tENABLE, TX EXTERNAL T/R CONTROL
tWAKE, SD, ST_ TO Tx MODE OR tENABLE, TX
tWAKE, SD, ST_ TO Rx MODE OR tENABLE, RX
T/R
Tx - > Rx
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參數(shù)描述
MAX19705ETM+ 功能描述:ADC / DAC多通道 7.5Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19705ETM+GH7 功能描述:ADC / DAC多通道 10-Bit 7.5Msps Ultra-Low-Power Analog Front-End RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19705ETM+T 功能描述:ADC / DAC多通道 7.5Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19705ETM+TGH7 功能描述:ADC / DAC多通道 10-bit 7.5Msps Ultra-Low-Power Analog Front-End RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19705ETM-T 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
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