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參數(shù)資料
| 型號： | MAX19705ETM+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 26/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANLG FRNT END 48-TQFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 43 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 4 |
| 功率（瓦特）： | 28.2mW |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.3 V |
| 電壓 - 電源，數(shù)字： | 1.8 V ~ 3.3 V |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-TQFN-EP（7x7） |
| 包裝： | 管件 |
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MAX19705
10-Bit, 7.5Msps, Ultra-Low-Power
Analog Front-End
32
______________________________________________________________________________________
0
2
1
4
3
7
6
5
000
010
001
011
100
101
110
AT STEP
011 (0.5 LSB)
AT STEP
001 (0.25 LSB)
111
DIGITAL INPUT CODE
ANALOG
OUTPUT
VALUE
Figure 13a. Integral Nonlinearity
0
2
1
4
3
6
5
000
010
001
011
100
101
DIFFERENTIAL LINEARITY
ERROR (-0.25 LSB)
DIFFERENTIAL
LINEARITY ERROR (+0.25 LSB)
1 LSB
DIGITAL INPUT CODE
ANALOG
OUTPUT
VALUE
Figure 13b. Differential Nonlinearity
Grounding, Bypassing, and
Board Layout
The MAX19705 requires high-speed board layout design
techniques. Refer to the MAX19705 EV kit data sheet for
a board layout reference. Place all bypass capacitors as
close to the device as possible, preferably on the same
side of the board as the device, using surface-mount
devices for minimum inductance. Bypass VDD to GND
with a 0.1F ceramic capacitor in parallel with a 2.2F
capacitor. Bypass OVDD to OGND with a 0.1F ceramic
capacitor in parallel with a 2.2F capacitor. Bypass
REFP, REFN, and COM each to GND with a 0.33F
ceramic capacitor. Bypass REFIN to GND with a 0.1F
capacitor.
Multilayer boards with separated ground and power
planes yield the highest level of signal integrity. Use a
split ground plane arranged to match the physical loca-
tion of the analog ground (GND) and the digital output-
driver ground (OGND) on the device package.
Connect the MAX19705 exposed backside paddle to
GND plane. Join the two ground planes at a single
point so the noisy digital ground currents do not inter-
fere with the analog ground plane. The ideal location
for this connection can be determined experimentally
at a point along the gap between the two ground
planes. Make this connection with a low-value, surface-
mount resistor (1
to 5), a ferrite bead, or a direct
short. Alternatively, all ground pins could share the
same ground plane, if the ground plane is sufficiently
isolated from any noisy digital system’s ground plane
(e.g., downstream output buffer or DSP ground plane).
Route high-speed digital signal traces away from sensi-
tive analog traces. Make sure to isolate the analog
input lines to each respective converter to minimize
channel-to-channel crosstalk. Keep all signal lines
short and free of 90° turns.
Dynamic Parameter Definitions
ADC and DAC Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the device are measured using
the best-straight-line fit (DAC Figure 13a).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes (ADC) and a monotonic transfer function
(ADC and DAC) (DAC Figure 13b).
ADC Offset Error
Ideally, the midscale transition occurs at 0.5 LSB above
midscale. The offset error is the amount of deviation
between the measured transition point and the ideal
transition point.
DAC Offset Error
Offset error (Figure 13a) is the difference between the
ideal and actual offset point. The offset point is the out-
put value when the digital input is midscale. This error
affects all codes by the same amount and usually can
be compensated by trimming.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX19705ETM+ | 功能描述:ADC / DAC多通道 7.5Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19705ETM+GH7 | 功能描述:ADC / DAC多通道 10-Bit 7.5Msps Ultra-Low-Power Analog Front-End RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19705ETM+T | 功能描述:ADC / DAC多通道 7.5Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19705ETM+TGH7 | 功能描述:ADC / DAC多通道 10-bit 7.5Msps Ultra-Low-Power Analog Front-End RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19705ETM-T | 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
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