MAX19710
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL
≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP = CREFN = CCOM = 0.33F, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SPI3-Rx mode: fCLK = 7.5MHz, fIN =
1.875MHz on both channels; Tx DAC ON
(Tx DAC outputs at midscale); aux-DACs
ON and at midscale, aux-ADC ON
9.5
12
Standby mode: CLK = 0 or OVDD;
aux-DACs ON and at midscale,
aux-ADC ON
2.7
3.5
Idle mode: fCLK = 7.5MHz; aux-DACs ON
and at midscale, aux-ADC ON
4.6
6
mA
VDD Supply Current
Shutdown mode: CLK = 0 or OVDD, or
aux-ADC OFF
0.5
5
A
FD mode: fCLK = 7.5MHz, fOUT = 620kHz
on both DAC channels; fIN = 1.875MHz on
both ADC channels; aux-DACs ON and at
midscale, aux-ADC ON
0.94
SPI1-Rx and SPI3-Rx modes: fCLK =
7.5MHz, fIN = 1.875MHz on both ADC
channels; DAC input bus tri-stated; aux-
DACs ON and at midscale, aux-ADC ON
0.90
mA
SPI2-Tx and SPI4-Tx modes: fCLK =
7.5MHz, fOUT = 620kHz on both DAC
channels; ADC output bus tri-stated; aux-
DACs ON and at midscale, aux-ADC ON
52
Standby mode: CLK = 0 or OVDD; aux-
DACs ON and at midscale, aux-ADC ON
0.1
Idle mode: fCLK = 7.5MHz; aux-DACs ON
and at midscale, aux-ADC ON
12.8
OVDD Supply Current
Shutdown mode: CLK = 0 or OVDD, or
aux-ADC OFF
0.1
A
Rx ADC DC ACCURACY
Resolution
N
10
Bits
Integral Nonlinearity
INL
±0.5
LSB
Differential Nonlinearity
DNL
No missing codes over temperature (Note 2)
-0.8
±0.4
+1.0
LSB
Offset Error
Residual DC offset error
-5
±0.2
+5
%FS
Gain Error
Includes reference error
-5
±0.9
+5
%FS
DC Gain Matching
-0.15
±0.04
+0.15
dB
Offset Matching
±11
LSB
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
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