參數(shù)資料
型號： MAX2079CXE+T
廠商： Maxim Integrated Products
文件頁數(shù)： 27/49頁
文件大小： 0K
描述： IC OCT ULTRASOUND RCVR 144CTBGA
標(biāo)準(zhǔn)包裝： 1,000
系列： *
Low-Power, High-Performance, Fully Integrated
Octal Ultrasound Receiver (Octal LNA, VGA,
AAF, ADC, and CWD Beamformer)
MAX2079
33
Maxim Integrated
sleep mode and nap mode. The device cannot enter
either of these states unless no ADC channels are active
in the current power state (Table 6).
In nap mode, the reference, duty-cycle equalizer, and
clock-multiplier PLL circuits remain active for rapid wake-
up time. In nap mode, the externally applied clock signal
must remain active for the duty-cycle equalizer and PLL
to remain locked. Typical wake-up time from nap mode
is 2Fs.
In sleep mode, all circuits are turned off except for the
bandgap voltage-generation circuit. All registers retain
previously programmed values during sleep mode.
Typical wake-up time from sleep mode is 2ms (typ).
Power-On and Reset
The user-programmable register default settings and
other factory-programmed settings are stored in a non-
volatile memory. Upon device power-up, these values are
loaded into the control registers. The operation occurs
after the application of a valid supply voltage to AVDD
and OVDD, and the presence of an input clock signal.
The user-programmed register values are retained as
long as the AVDD and OVDD voltages are applied.
A reset condition overwrites all user-programmed regis-
ters with the factory-default values. The reset condition
occurs on power-up and can be initiated while powered
with a software write command (write 5Ah) through the
serial-port interface to the Special Function register
(10h). The reset time is proportional to the ADC clock
period and requires 415Fs at 50Msps.
Power-Down and Low-Power (Nap)
Mode and Channel Selection
The SHDN pin is a toggle switch between any two power-
management states. In most cases, the SHDN = 0 state
is on, and the SHDN = 1 state is off. However, complete
flexibility is provided, allowing the user to toggle between
active and nap, active and sleep, etc. Nap mode is
defined as a reduced-power state with rapid wake-up
time on the order of 2Fs. Sleep mode is a very-low-power
mode (~1mW) with a much longer wake-up time on the
order of 2ms. The serial port and programmable registers
remain active during nap and sleep modes.
CHn_ON_SHDN0 n = [1:8]
1 Channel n is on when the SHDN pin is low.
0 Channel n is off when the SHDN pin is low.
CHn_ON_SHDN1 n = [1:8]
1 Channel n is on when the SHDN pin is high.
0 Channel n is off when the SHDN pin is high.
ADC_NAP_SHDN0
1 ADC in nap mode when all channels are off, or the
CWD pin is high and the SHDN pin is low.
0 ADC in sleep mode when all channels are off, or
the CWD pin is high and the SHDN pin is low.
ADC_NAP_SHDN1
1 ADC in nap mode when all channels are off, or the
CWD pin is high and the SHDN pin is high.
0 ADC in sleep mode when all channels are off, or
the CWD pin is high and the SHDN pin is high.
AFe_NAP_SHDN0
1 AFE in nap mode when all channels are off and the
SHDN pin is low.
0 AFE in sleep mode when all channels are off and
the SHDN pin is low.
AFe_NAP_SHDN1
1 AFE in nap mode when all channels are off and the
SHDN pin is high.
0 AFE in sleep mode when all channels are off and
the SHDN pin is high.
3-Wire Serial Peripheral Interface (SPI)
The ADC operates as a slave device that sends and
receives data through a 3-wire SPI interface. A mas-
ter device must initiate all data transfers to and from
the device. The device uses an active-low SPI chip-
select input (CS) to enable communication with timing
controlled through the externally generated SPl clock
input (SCLK). All data is sent and received through the
bidirectional SPI data line (SDIO). The device has 16
user-programmable control registers and one special-
function register, which are accessed and programmed
through this interface.
SPI Communication Format
Figure 20 shows an ADC SPI communication cycle. All
SPI communication cycles are made up of 2 bytes of
data on SDIO and require 16 clock cycles on SCLK to
be completed. To initiate an SPI read or write commu-
nication cycle, CS must first transition from a logic-high
to a logic-low state. While CS remains low, serial data
is clocked in from SDIO on rising edges of SCLK, and
clocked out (for a read) on the falling edges of SCLK.
When CS is high, the device does not respond to SCLK
transitions, and no data is read from or written to SDIO.
CS must transition back to logic-high after each read/
write cycle is completed.
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