參數(shù)資料
型號(hào)： MAX2079CXE+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 28/49頁(yè)
文件大?。?/td> 0K
描述： IC OCT ULTRASOUND RCVR 144CTBGA
標(biāo)準(zhǔn)包裝： 1,000
系列： *
Low-Power, High-Performance, Fully Integrated
Octal Ultrasound Receiver (Octal LNA, VGA,
AAF, ADC, and CWD Beamformer)
MAX2079
34
Maxim Integrated
Figure 20. SPI Timing Diagram
The first byte transmitted on SDIO is always provided by
the master. The ADC (slave device) clocks in the data
from SDIO on each rising edge of SCLK. The first bit
received selects whether the communication cycle is a
read or a write. Logic 1 selects a read cycle, while logic
0 selects a write cycle. The next 7 bits (MSB first) are the
register address for the read or write cycle. The address
can indicate any of the 16 user-programmable control
registers (00h to 0Fh), or the special-function register
(10h, write only). Attempting to read/write with any other
address has no effect (Table 3).
The second byte on SDIO is sent to the ADC in the case
of a write, or received from the ADC in the case of a read.
For a write command, the device continues to clock in the
data on SDIO on each rising edge of SCLK. In the case
of a read command, the device writes data to SDIO on
each falling edge of SCLK. The data byte is transmitted
and received MSB first in both cases. The detailed SPI
timing requirements are shown in Figure 20.
tCSS
tCSH
tSCLK
tSDS
tSDH
tSDD
CS
SCLK
SDIO
CS
SCLK
SDIO
R/WA6A5A4A3A2A1A0D7D6D5D4D3D2D1D0
WRITE
ADDRESS
DATA
WRITE OR READ
READ
tSCLK—SCLK PERIOD
tCSS—SCLK-TO-CS SETUP TIME
tCSH—SCLK-TO-CS HOLD TIME
tSDS—SDIO-TO-SCLK SETUP TIME
tSDH—SDIO-TO-SCLK HOLD TIME
tSDD—SCLK-TO-SDIO OUTPUT DATA DELAY
R / W
0 = WRITE
1 = READ
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