參數(shù)資料
型號(hào)： MAX2079CXE+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 40/49頁(yè)
文件大?。?/td> 0K
描述： IC OCT ULTRASOUND RCVR 144CTBGA
標(biāo)準(zhǔn)包裝： 1,000
系列： *
Low-Power, High-Performance, Fully Integrated
Octal Ultrasound Receiver (Octal LNA, VGA,
AAF, ADC, and CWD Beamformer)
MAX2079
45
Maxim Integrated
Table 42. Status Byte (Reads from 10h)
Table 43. SPI Commands (Writes to 10h)
(All commands are issued by writing SPI address 10h.)
Soft Reset
Software reset allows the user to reset the part through
writes to the serial port. A soft reset can be performed by
writing the reset code 5Ah to address 10h. Upon initiation
of soft reset, the fuse memory is read and loaded into the
SPI registers. See the 3-Wire Serial Peripheral Interface
(SPI) section for further detail. The reset is self-clearing,
subsequent serial-port write(s) are not needed to clear
the reset condition.
AFE Programming and Data Transfer
The internal analog front-end (AFE) and ADC are pro-
grammed through a common serial-port interface. There
are 48 user-programmable bits in the ADC that store AFE
control information. These bits are written to registers
0Ah to 0Fh in the ADC, and transferred to the AFE shift
registers when AEh is written to register 10h. The user
must provide at least 50 clock cycles on SCLK after this
control word is written to complete the data transfer to the
AFE. To verify that the data has been transferred to the
AFE, poll address 10h until bit 6 is 0. As a final step, write
00h to address 10h. Changes in registers 0Ah to 0Fh do
not take effect in the AFE until this transfer is complete.
CWD Beamformer
Programming and Clocking
Programming of the CWD beamformer occurs in the
following sequence:
1) During normal CWD mode, the mixer clock (LO+, LO-)
is on. LOON is high.
2) Shut off the mixer clock (LO+, LO-) or pull LOON low
to start the programming sequence.
3) Write the phase and channel shutdown information
into the proper control registers.
4) Transfer the phase information from the control reg-
isters to the AFE (see above) and wait for the write
to complete. Turn on the mixer clock and set LOON
to high to start beamforming (the AFE shift registers
can also be written with the mixer clock running and
LOON set low). If turning on the mixer clock source,
the clock must turn on such that it starts at the begin-
ning of a mixer clock cycle. A narrow glitch on the
mixer clock is not acceptable and could cause meta-
stability in the I/Q phase dividers. If using the LOON
control to turn on the mixer clock, the LOON signal
must be synchronous to the LO clock, and it must
meet the minimum setup time specification.
STATUS BIT NO.
ReAD VALUe
DeSCRIPTION
7
0
Reserved
6
0
1 = AFE load in progress; 0 = load complete
5
0 or 1
1 = ROM read in progress
4
0 or 1
1 = ROM read completed, and register data is valid (checksum ok)
3
0
Reserved
2
1
Reserved
1
0 or 1
Reserved
0
0 or 1
1 = Duty-cycle equalizer DLL is locked
COMMAND
WRITe DATA
DeSCRIPTION
Soft reset
5Ah
Initiates software reset
Transfer data to AFE
AEh
Initiates transfer of data in ADC registers 0Ah to 0Fh to AFE
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