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參數(shù)資料
| 型號： | MAX9222EUM |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable DC-Balance 21-Bit Deserializers |
| 中文描述： | QUAD LINE RECEIVER, PDSO48 |
| 封裝： | 6.10 MM, MO-153ED, TSSOP-48 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 904K |
| 代理商： | MAX9222EUM |
M
Programmable DC-Balance
21-Bit Deserializers
10
______________________________________________________________________________________
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode voltage
range by AC-coupling. AC-coupling increases the com-
mon-mode voltage range of an LVDS receiver to nearly
the voltage rating of the capacitor. The typical LVDS dri-
ver output is 350mV centered on an offset voltage of
1.25V, making single-ended output voltages of 1.425V
and 1.075V. An LVDS receiver accepts signals from 0 to
2.4V, allowing approximately
±
1V common-mode differ-
ence between the driver and receiver on a DC-coupled
link (2.4V - 1.425V = 0.975V and 1.075V - 0V = 1.075V).
Common-mode voltage differences may be due to
ground potential variation or common-mode noise. If
there is more than
±
1V of difference, the receiver is not
guaranteed to read the input signal correctly and may
cause bit errors. AC-coupling filters low-frequency
ground shifts and common-mode noise and passes
high-frequency data. A common-mode voltage differ-
ence up to the voltage rating of the coupling capacitor
(minus half the differential swing) is tolerated. DC-bal-
anced coding of the data is required to maintain the dif-
ferential signal amplitude and limit jitter on an
AC-coupled link. A capacitor in series with each output
of the LVDS driver is sufficient for AC-coupling.
However, two capacitors—one at the serializer output
and one at the deserializer input—provide protection in
case either end of the cable is shorted to a high voltage.
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols
cause signal transitions to start from different voltage
levels. Because the transition time is finite, starting the
signal transition from different voltage levels causes
timing jitter. The time constant for an AC-coupled link
needs to be chosen to reduce droop and jitter to an
acceptable level.
7 : 1
1 : 7
7
7
100
7 : 1
1 : 7
7
7
100
7 : 1
1 : 7
7
7
100
PLL
PLL
100
MAX9209
MAX9211
MAX9213
MAX9215
MAX9210
MAX9212
MAX9214
MAX9216
MAX9220
MAX9222
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
TRANSMISSION LINE
Figure 11. DC-Coupled Link, Non-DC-Balanced Mode
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9222EUM+ | 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Rail/Tube |
| MAX9222EUM+D | 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Rail/Tube |
| MAX9222EUM+T | 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Tape and Reel |
| MAX9222EUM+TD | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
| MAX9222EUM-D | 制造商:Maxim Integrated Products 功能描述:PROGRAMMABLE DC-BALANCE 21-BIT DESERIALIZERS - Rail/Tube |
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