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參數(shù)資料
| 型號： | MAX9222EUM |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable DC-Balance 21-Bit Deserializers |
| 中文描述： | QUAD LINE RECEIVER, PDSO48 |
| 封裝： | 6.10 MM, MO-153ED, TSSOP-48 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 904K |
| 代理商： | MAX9222EUM |
M
Programmable DC-Balance
21-Bit Deserializers
8
_______________________________________________________________________________________
IDEAL
MIN
MAX
INTERNAL STROBE
IDEAL
RSKM
RSKM
IDEAL SERIAL BIT TIME
1.3V
1.1V
Figure 4. LVDS Receiver Input Skew Margin
RxOUT_
RxCLK OUT
RCIP
RCOH
RCOL
2.0V
0.8V
2.0V
0.8V
2.0V
2.0V
2.0V
0.8V
0.8V
RHRC
RSRC
Figure 5a. Rising-Edge Output Setup/Hold and High/Low Times
RxOUT_
RxCLK OUT
RCIP
RCOH
RCOL
2.0V
0.8V
2.0V
0.8V
2.0V
2.0V
0.8V
0.8V
0.8V
RHRC
RSRC
Figure 5b. Falling-Edge Output Setup/Hold and High/Low Times
V
ID
= 0
1.5V
RCCD
RxCLK IN
RxCLK OUT
Figure 6a. Rising-Edge Clock-IN to Clock-OUT Delay
RxCLK IN
RxCLK OUT
+
-
RCCD
1.5V
V
ID
= 0
Figure 6b. Falling-Edge Clock-IN to Clock-OUT Delay
90%
90%
10%
10%
CHLT
CLHT
RxOUT_ OR
RxCLK OUT
RxOUT_ OR
RxCLK OUT
8pF
Figure 3. Output Load and Transition Times
PWRDWN
V
CC
RxCLK IN
RxCLK OUT
3V
2V
RPLLS
HIGH-Z
Figure 7. Phase-Locked Loop Set Time
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9222EUM+ | 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Rail/Tube |
| MAX9222EUM+D | 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Rail/Tube |
| MAX9222EUM+T | 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Tape and Reel |
| MAX9222EUM+TD | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
| MAX9222EUM-D | 制造商:Maxim Integrated Products 功能描述:PROGRAMMABLE DC-BALANCE 21-BIT DESERIALIZERS - Rail/Tube |
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