參數(shù)資料
型號(hào): MAX9257GTL+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/52頁(yè)
文件大小: 0K
描述: IC SER/DESER PROG 40-TQFN
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 串行器/解串器
數(shù)據(jù)速率: 840Mbps
輸入類(lèi)型: 串行
輸出類(lèi)型: LVDS
輸入數(shù): 16
輸出數(shù): 1
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX9257/MAX9258
10
______________________________________________________________________________________
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
MAX9257 Pin Description
PIN
TQFN
LQFP
NAME
FUNCTION
1, 18
2, 21
VCCIO
Single-Ended Input/Output Buffer Supply Voltage. Bypass VCCIO to GND with 0.1F and
0.001F capacitors in parallel as close as possible to the device with the smallest value
capacitor closest to VCCIO.
2, 11,
19, 34
3, 14,
22, 41
GND
Digital Supply Ground
3–8
4–9
DIN[9:14]/
GPIO[1:6]
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits
word length, DIN_ not programmed as data inputs becomes GPIO (Table 22). DIN[9:14]
are internally pulled down to ground.
9
10
GNDFPLL
Filter PLL Ground
10
11
VCCFPLL
Filter PLL Supply Voltage. Bypass VCCFPLL to GNDFPLL with 0.1F and 0.001F capacitors
in parallel as close as possible to the device with the smallest value capacitor closest to
VCCFPLL.
12
15
DIN15/GPIO7
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits
word length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN15 is
internally pulled down to ground.
13
16
HSYNC_IN
Horizontal SYNC Input. HSYNC_IN is internally pulled down to ground.
14
17
VSYNC_IN
Vertical SYNC Input. VSYNC_IN is internally pulled down to ground.
15
18
PCLK_IN
Parallel Clock Input. PCLK_IN latches data and sync inputs and provides the PLL reference
clock. PCLK_IN is internally pulled down to ground.
16
19
SCL/TX
Open-Drain Control Channel Output. SCL/TX becomes SCL output when UART-to-I2C is
active. SCL/TX becomes TX output when UART-to-I2C is bypassed. Externally pull up to VCC.
17
20
SDA/RX
Open-Drain Control Channel Input/Output. SDA/RX becomes bidirectional SDA when
UART-to-I2C is active. SDA/RX becomes RX input when UART-to-I2C is bypassed. SDA
output requires a pullup to VCC.
20, 33
23, 40
VCC
Digital Supply Voltage. Bypass VCC to ground with 0.1F and 0.001F capacitors in parallel
as close as possible to the device with the smallest value capacitor closest to VCC.
21
26
GPIO8
General Purpose Input/Output
22
27
GPIO9
General Purpose Input/Output
23
28
VCCSPLL
Spread PLL Supply Voltage. Bypass VCCSPLL to GNDSPLL with 0.1F and 0.001F
capacitors in parallel as close as possible to the device with the smallest value capacitor
closest to VCCSPLL.
24
29
GNDSPLL
SPLL Ground
25
30
GNDLVDS
LVDS Ground
26
31
SDO-
Serial LVDS Inverting Output
27
32
SDO+
Serial LVDS Noninverting Output
28
33
VCCLVDS
LVDS Supply Voltage. Bypass VCCLVDS to GNDLVDS with 0.1F and 0.001F capacitors in
parallel as close as possible to the device with the smallest value capacitor closest to
VCCLVDS.
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