參數(shù)資料
型號(hào): MAX9257GTL+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 3/52頁(yè)
文件大小: 0K
描述: IC SER/DESER PROG 40-TQFN
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 串行器/解串器
數(shù)據(jù)速率: 840Mbps
輸入類型: 串行
輸出類型: LVDS
輸入數(shù): 16
輸出數(shù): 1
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX9257/MAX9258
______________________________________________________________________________________
11
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
MAX9257 Pin Description (continued)
PIN
TQFN
LQFP
NAME
FUNCTION
29
34
REM
Remote Power-Up/Power-Down Select Input. Connect REM to ground for power-up to
follow VCC. Connect REM high to VCC through 10k
Ω resistor for remote power-up. REM is
internally pulled down to GND.
30, 31, 32,
35–39
35, 38,
39, 42–46
DIN[0:7]
Data Inputs. DIN[0:7] are internally pulled down to ground.
40
47
DIN8/GPIO0
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits
word length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN8 is
internally pulled down to ground.
1, 12, 13
24, 25,
36, 37, 48
N.C.
No Connection. Not internally connected.
EP
Exposed Pad for Thin QFN Package Only. Connect EP to ground.
MAX9258 Pin Description
PIN
NAME
FUNCTION
1, 12, 13, 24,
25, 36,
37
N.C.
No Connection. Not internally connected.
2VCC
Digital Supply Voltage. Bypass VCC to GND with 0.1F and 0.001F capacitors in parallel as close
as possible to the device with the smallest value capacitor closest VCC.
3, 14
GND
Digital Supply Ground
4
PD
LVCMOS/LVTTL Power-Down Input. Drive
PD high to power up the device and enable all outputs.
Drive
PD low to put all outputs in high impedance and reduce supply current. PD is internally pulled
down to ground.
5VCCLVDS
LVDS Supply Voltage. Bypass VCCLVDS to GNDLVDS with 0.1F and 0.001F capacitors in parallel
as close as possible to the device with the smallest value capacitor closest to VCCLVDS.
6
SDI-
Serial LVDS Inverting Input
7
SDI+
Serial LVDS Noninverting Input
8
GNDLVDS
LVDS Supply Ground
9
GNDPLL
PLL Supply Ground
10
VCCPLL
PLL Supply Voltage. Bypass VCCPLL to GNDPLL with 0.1F and 0.001F capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to VCCPLL.
11
ERROR
Active-Low, Open-Drain Error Output.
ERROR asserts low to indicate a data transfer error was
detected (parity, PRBS, or UART control channel error).
ERROR is high to indicate no error detected.
ERROR resets when the error registers are read for parity, control channel errors, and when PRBS
enable bit is reset for PRBS errors. Pull up to VCCOUT with a 1k
Ω resistor.
15
RX
LVCMOS/LVTTL Control Channel UART Output
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