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參數(shù)資料
| 型號： | MAX9880AEWM+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO STEREO 48WLP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | I²C，I²S，串行，SPI? |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 82 / 96 |
| 電壓 - 電源，模擬： | 1.65 V ~ 1.95 V |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 1.95 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFBGA，WLCSP |
| 供應(yīng)商設(shè)備封裝： | 48-WLP（2.70x3.50） |
| 包裝： | 帶卷 (TR) |
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MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________
25
Pin Description (continued)
PIN
TQFN-EP
WLP
NAME
FUNCTION
23
E8
LINL
Left-Line Input. AC-couple analog audio signal to LINL with a 1F capacitor.
24
F8
LINR
Right-Line Input. AC-couple analog audio signal to LINR with a 1F capacitor.
25
F7
LOUTR
Right-Line Output
26
E7
LOUTL
Left-Line Output
27
E6, F6
PGND
Headphone Power Ground
29
E5
ROUTP
Positive Right-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
30
F5
ROUTN
Negative Right-Channel Headphone Output. Unused in capacitorless and
single-ended mode.
31
F4
LOUTN
Negative Left-Channel Headphone Output. Common headphone return in
capacitorless mode. Unused in single-ended mode.
32
E4
LOUTP
Positive Left-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
34
E3, F3
PVDD
Headphone Power Supply. Bypass to PGND with a 1F capacitor.
36
F2
DVDDS1
S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1F
capacitor.
37
F1
SDOUTS1
S1 Digital Audio Serial-Data ADC Output
38
D3
SDINS1
S1 Digital Audio Serial-Data DAC Input
39
E1
LRCLKS1
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample
rate clock and determines whether the audio data on SDINS1 is routed to the left
or right channel. In TDM mode, LRCLKS1 is a frame sync pulse. LRCLKS1 is an
input when the MAX9880A is in slave mode and an output when in master
mode.
40
E2
BCLKS1
S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the
MAX9880A is in slave mode and an output when in master mode.
41
D1
MCLK
Master Clock Input. Acceptable input frequency range: 10MHz to 60MHz.
42
D2
SDOUTS2
S2 Digital Audio Serial-Data ADC Output
43
C1
SDINS2
S2 Digital Audio Serial-Data DAC Input
44
C2
LRCLKS2
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample
rate clock and determines whether the audio data on SDINS2 is routed to the left
or right channel. In TDM mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an
input when the MAX9880A is in slave mode and an output when in master
mode.
45
C3
BCLKS2
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the
MAX9880A is in slave mode and an output when in master mode.
46
B1
DVDD
Digital Power Supply. Supply for the digital core and I2C/SPI interface. Bypass to
DGND with a 1.0F capacitor.
47
A1
DGND
Digital Ground
—
EP
Exposed Pad. Connect the exposed thermal pad to AGND.
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