Dual I2S Stereo Audio Codec 10 ____________" />
參數(shù)資料
型號: MAX9880AEWM+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/70頁
文件大小: 0K
描述: IC CODEC AUDIO STEREO 48WLP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 立體聲音頻
數(shù)據(jù)接口: I²C,I²S,串行,SPI?
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 82 / 96
電壓 - 電源,模擬: 1.65 V ~ 1.95 V
電壓 - 電源,數(shù)字: 1.65 V ~ 1.95 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFBGA,WLCSP
供應(yīng)商設(shè)備封裝: 48-WLP(2.70x3.50)
包裝: 帶卷 (TR)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
10
______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL =
∞, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT CLOCK CHARACTERISTICS
MCLK Input Frequency
fMCLK
For any LRCLK sample rate
10
60
MHz
Prescaler = /1 mode
40
60
MCLK Input Duty Cycle
/2 or /4 modes
30
70
%
Maximum MCLK Input
Jitter
Maximum allowable RMS for performance limits
100
ps
DHF = 0
8
48
LRCLK Sample Rate
(Note 10)
DHF = 1
48
96
kHz
FREQ1 mode = 0x8 to 0xF
0
PCLK = 192x, 256x, 384x, 512x, 768x, and 1024x
0
LRCLK Average
Frequency Error (Master
and Slave Modes)
(Note 11)
FREQ1 mode = Any clock other than above
-0.025
+0.025
%
Rapid lock mode
2
7
LRCLK PLL Lock Time
Any allowable LRCLK and
PCLK rate, slave mode
Nonrapid lock mode
12
25
ms
LRCLK Acceptable
Jitter for Maintaining
PLL Lock
Allowable LRCLK period change from nominal for
slave PLL mode at any allowable LRCLK and PCLK
rates
±100
ns
Soft-Start/Stop Time
10
ms
CRYSTAL OSCILLATOR
Frequency
Fundamental mode only
12.288
MHz
Maximum Crystal ESR
100
Input Leakage Current
IIH, IIL
X1, TA = +25°C
-1
+1
A
Input Capacitance
CX1, CX2
4
pF
Maximum Load
Capacitor
CL1, CL2
45
pF
DIGITAL INPUT (MCLK)
Input High Voltage
VIH
1.2
V
Input Low Voltage
VIL
0.6
V
Input Leakage Current
IIH, IIL
TA = +25°C
-1
+1
A
Input Capacitance
10
pF
DIGITAL INPUTS (SDINS1, BCLKS1, LRCLKS1)
Input High Voltage
VIH
0.7
x VDVDDS1
V
Input Low Voltage
VIL
0.3
x VDVDDS1
V
Input Hysteresis
200
mV
Input Leakage Current
IIH, IIL
TA = +25°C
-1
+1
A
Input Capacitance
10
pF
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