參數(shù)資料
型號: MAX9967BRCCQ+D
廠商: Maxim Integrated Products
文件頁數(shù): 13/30頁
文件大?。?/td> 0K
描述: IC DCL DUAL 500MBPS ATE 100TQFP
標準包裝: 90
系列: ATE
邏輯類型: 比較器, 驅動器
電源電壓: -1.5 V ~ 6.5 V
位數(shù): 2
工作溫度: 0°C ~ 70°C
安裝類型: *
封裝/外殼: *
供應商設備封裝: *
包裝: *
MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
20
______________________________________________________________________________________
Detailed Description
The MAX9967 dual, low-power, high-speed, pin elec-
tronics DCL IC includes, for each channel, a three-level
pin driver, a dual comparator, variable clamps, and an
active load. The driver features a -1.5V to +6.5V operat-
ing range and high-speed operation, includes high-
impedance and active-termination (3rd-level drive)
modes, and is highly linear even at low voltage swings.
The dual comparator provides low dispersion (timing
variation) over a wide variety of input conditions. The
clamps provide damping of high-speed DUT_ wave-
forms when the device is configured as a high-imped-
ance receiver. The programmable load supplies up to
35mA of source and sink current. The load facilitates
contact/continuity testing, at-speed parametric testing
of IOH and IOL, and pullup of high output-impedance
devices.
The MAX9967A provides tight matching of gain and off-
set for the drivers and offset for the comparators and
active load, allowing reference levels to be shared
across multiple channels in cost-sensitive systems. Use
the MAX9967B for system designs that incorporate
independent reference levels for each channel.
Optional internal resistors at the high-speed inputs pro-
vide compatibility with ECL, LVPECL, LVDS, and GTL
interfaces. Connect the termination voltage inputs
(TDATA_, TRCV_, TLDEN_) to the appropriate voltage
for terminating ECL, LVPECL, GTL, or other logic.
Leave the inputs unconnected for 100
differential
LVDS termination. In addition, ECL/LVPECL or flexible
open-collector outputs with optional internal pullup
resistors are available for the comparators. These fea-
tures significantly reduce the discrete component count
on the circuit board.
A 3-wire, low-voltage, CMOS-compatible serial inter-
face programs the low-leakage, load-disable, slew-rate,
and tri-state/terminate operational configurations of the
MAX9967.
Output Driver
The driver input is a high-speed multiplexer that selects
one of three voltage inputs: DHV_, DLV_, or DTV_. This
switching is controlled by high-speed inputs DATA_ and
RCV_ and mode control bit TMSEL (Table 1). A slew-rate
circuit controls the slew rate of the buffer input. Select one
of four possible slew rates according to Table 2. The
speed of the internal multiplexer sets the100% driver slew
rate (see the Driver Large-Signal Response graph in the
Typical Operating Characteristics).
PIN
NAME
FUNCTION
88
VCCO1
Channel 1 Collector Voltage Input. Voltage for channel 1 comparator output pullup resistors. For
open-collector outputs, this is the pullup voltage for the internal termination resistors. For open-
emitter outputs, this is the collector voltage of the output transistors. Not internally connected on
open-collector versions without internal termination resistors.
89
CH1
90
NCH1
Channel 1 High Comparator High Output. Differential output of channel 1 high-side comparator.
94
CPHV1
Channel 1 High-Clamp Reference Input
95
CPLV1
Channel 1 Low-Clamp Reference Input
96
DHV1
Channel 1 Driver High Reference Input
97
DTV1
Channel 1 Driver Termination Reference Input
98
DLV1
Channel 1 Driver Low Reference Input
99
CHV1
Channel 1 High-Comparator Reference Input
100
CLV1
Channel 1 Low-Comparator Reference Input
Pin Description (continued)
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