MAX9967
Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
10
______________________________________________________________________________________
Note 1: All minimum and maximum limits are 100% production tested. Tests are performed at nominal supply voltages unless oth-
erwise noted.
Note 2: Total for dual device at worst-case setting. RL > 10M
. The supply currents are measured with typical supply voltages.
Note 3: Does not include internal dissipation of the comparator outputs. With output loads of 50
to (VVCCO - 2V), this adds 120mW
(typ) to the total device power (MAX9967_MCCQ and MAX9967_QCCQ). For MAX9967_LCCQ, additional power dissipa-
tion is typically (32mA x VVCCO).
Note 4: Externally forced voltages may exceed this range provided that the Absolute Maximum Ratings are not exceeded.
Note 5: Transition time from LLEAK being asserted to leakage current dropping below specified limits.
Note 6: Based on simulation results only.
Note 7: Transition time from LLEAK being deasserted to output returning to normal operating mode.
Note 8: With the exception of Offset and Gain/CMRR tests, reference input values are calibrated for offset and gain.
Note 9: Measured at VCC = +9.75, VEE = -5.25V, and TJ = +85°C.
Note 10: Relative to straight line between 0 and 4.5V.
Note 11: Specifications measured at the end points of the full range. Full ranges are -1.3V
≤ VDHV_ ≤ 6.5V, -1.5V ≤ VDLV_ ≤ 6.3V,
-1.5V
≤ VDTV_ ≤ 6.5V.
Note 12: Change in offset voltage with power supplies independently set to their minimum and maximum values.
Note 13: Nominal target value is 50
. Contact factory for alternate trim selections within the 45 to 51 range.
Note 14: VDTV_ = +1.5V, RS = 50
. External signal driven into T-line is a 0 to +3V edge with 1.2ns rise time (10% to 90%).
Measurement is made using the comparator.
Note 15: Measured from the crossing point of DATA_ inputs to the settling of the driver output.
Note 16: Prop delays are measured from the crossing point of the differential input signals to the 50% point of the expected output
swing. Rise time of differential inputs DATA_ and RCV_ is 250ps (10% to 90%).
Note 17: Rising edge to rising edge or falling edge to falling edge.
Note 18: Specified amplitude is programmed. At this pulse width, the output reaches at least 95% of its nominal (DC) amplitude. The
pulse width is measured at DATA_.
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0,
TJ = +85
°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VLDH_ = 100mV, 1V, 2.5V
±60
Sink Current Linearity
(Note 26)
VLDH_ = 3.5V
±130
A
GROUND SENSE
GS Voltage Range
VGS
Verified by GS common-mode error test
±250
mV
VDUT_ = -1.5V, VGS =
±250mV, VLDH_- VGS
= 0.1V
±25
GS Common-Mode Error
VDUT_ = +4.5V, VGS =
±250mV, VLDL_ -
VGS = 0.1V
±25
A
GS Input Bias Current
VGS = 0
±25
A
AC CHARACTERISTICS (ZL = 50
to GND)
ISOURCE = 20mA, VCOM_ = -1.5V
Enable Time (Note 27)
tEN
ISINK = 20mA, VCOM_ = +1.5V
2.2
ns
ISOURCE = 20mA, VCOM_ = -1.5V
Disable Time (Note 27)
tDIS
ISINK = 20mA, VCOM_ = +1.5V
1.9
ns
To 10%
10
Current Settling Time on
Commutation
ISOURCE = ISINK = 1mA and
35mA (Notes 7, 28)
To 1.5%
50
ns
Spike During Enable/Disable
Transition
ISOURCE = ISINK = 35mA, VCOM_ = 0
100
mV