5
MB582A/583A
I
PIN DESCRIPTION
MB582A (Transmitter)
(Continued)
Pin no.
Symbol
Pin name
I/O interface
(speed)
Function
24, 23
20 to 17,
14,13
D0 to D7
Parallel data
input
TTL input
<19.44
Mbyte/s>
Parallel data input pins:
fetched at the rising edge of the PICLK pulse or by
the internal parallel clock.
Parallel data D0 to D7 are
10
PICLK
Parallel clock
input
TTL input
<19.44 MHz>
Clock input pin for parallel data fetching:
Parallel data D0 to D7 are fetched at the rising edge
of the PICLK pulse. This pin is used for the clock
synthesizer. Connect a stable oscillator (such as a
crystal oscillator within
±
20 ppm) to this pin. This pin
is used when PCLKSEL = “0”. This pin can’t be used
when REFSEL = “0”.
9
PCLKSEL
Parallel clock
selection
TTL input
<0 or 1>
Clock selection pin for parallel data fetching:
The internal parallel clock and PICLK are selected
when this pin inputs “1” and “0,” respectively.
Also, this pin is used to select the reference clock for
the clock synthesizer. REFCLK and PICLK are
selected when this pin inputs “1” and “0”,
respectively.
46
REFCLK
Reference
clock input
TTL input
<19.44 or
51.84 MHz>
Reference clock input pin:
PLL circuit in the clock synthesizer. Connect a
stable oscillator (such as a crystal oscillator within
±
20 ppm) to this pin.
One of two reference clocks can be selected.
This pin is used when PCLKSEL = “1”.
This pin is used for the
32
REFSEL
Reference
clock
selection
TTL input
<0 or 1>
Reference clock selection pin:
The 19.44- and 51.84-MHz reference clocks are
selected when this pin inputs “1” and “0,”
respectively.
4
EXTCLK
External
clock input
PECL input
<up to
155.52 MHz>
Single PECL input pin:
frequency external clock signal to execute an 8-to-1
multiplexer function independent of the clock
synthesizer.
In this case, the operating frequency is free and may
be up to 155.52 MHz. This pin is used when
CLKSEL = “0”.
This pin inputs a high-