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參數(shù)資料
| 型號(hào)： | MB582A |
| 廠商： | Fujitsu Limited |
| 英文描述： | 155-Mbps ATM Transceiver(155Mbps 異步傳輸模式 收發(fā)器) |
| 中文描述： | 155 - Mbps的自動(dòng)柜員機(jī)收發(fā)器（155Mbps異步傳輸模式收發(fā)器） |
| 文件頁數(shù)： | 6/46頁 |
| 文件大?。?/td> | 345K |
| 代理商： | MB582A |
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6
MB582A/583A
(Continued)
(Continued)
Pin no.
Symbol
Pin name
I/O interface
(speed)
Function
3
CLKSEL
Clock
selection
TTL input
<0 or 1>
Clock selection pin:
The clock generated by the clock synthesizer and
the EXTCLK clock are selected when this pin inputs
“1” and “0,” respectively.
2
RESET
Reset input
Asynchronous reset input pin:
initialize the internal state. The internal circuit is
reset when this pin inputs “0”.
Upon reset, the TX-READY and POCLK pins output
Low-level signals. Also, the serial data output pins
DO and DO output Low- and High-level signals,
respectively.
The device must be reset when the power is turned
on. For details, see “POWER-ON RESET,P17.”
This pin is used to
5
PDOWN
Power down
TTL input
<0 or 1>
Sleep mode pin:
reduced to about 1/3 of normal level when this pin
inputs “1.” When it inputs “0,” the circuit restores
normal operation. In sleep mode, the TX-READY
and DO pins output Low-level signals; the DO and
POCLK pins output High-level signals. For details
on sleep mode, see “USING SLEEP MODE, P19.”
The circuit supply current is
39
41
DO
DO
Serial data
output
PECL output
<155.52
Mbps>
Serial data output pins:
coded serial data converted from parallel data in the
order of D7 to D0.
These pins output NRZ-
12
POCLK
Parallel clock
output
TTL output
<19.94 MHz>
Parallel clock output pin:
parallel clock synchronized with REFLCK. This
output pin can be connected to the controller
(MB86683 NTC).
This pin outputs a
25
TX-READY
Ready output
TTL output
<L or H>
Asynchronous READY output pin:
This pin indicates whether the MB582 is ready. The
pin outputs the High-level signal when the device is
in the ready state.
The pin does not indicate the ready state when; the
PICLK pulse is not input while PCLKSEL = “0”
(selecting PICLK for the parallel clock), RESET = “0”
(for reset operation), PDOWN = “1” (for sleep
mode), or the PLL circuit in the clock synthesizer is
not locked.
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