參數(shù)資料
型號: MB8116165A-60
廠商: Fujitsu Limited
英文描述: CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級頁面存取模式動態(tài)RAM)
中文描述: 的CMOS 100萬× 16位的超頁模式動態(tài)RAM的CMOS(100萬× 16位超級頁面存取模式動態(tài)內(nèi)存)
文件頁數(shù): 19/30頁
文件大小: 376K
代理商: MB8116165A-60
19
MB8116165A-60/MB8116165A-70
Fig. 11 – HYPER PAGE MODE READ CYCLE (WE = “H” or “L”)
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
LCAS
or
UCAS
WE
DQ
(Input)
A
0
to A
11
V
OH
V
OL
DQ
(Output)
V
IH
V
IL
OE
DESCRIPTION
The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row
address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level
during all successive memory cycles in which the row address is latched. The access time is determined by t
CAC
, t
AA
, t
CPA
, or t
OEA
,
whichever one is the latest in occurring.
t
RASP
t
CRP
t
ASR
t
ASC
t
RCS
t
RHCP
“H” or ”L”
t
RP
ROW
ADD
COL
ADD
t
CAS
t
RSH
t
HPC
t
CAS
t
CAS
t
DZC
t
CSH
t
CAH
t
RAH
t
CSH
t
ASC
t
RCH
Valid Data
t
AA
COL
ADD
t
CSH
t
RAL
HIGH-Z
t
OFF
t
OH
t
OEZ
t
OED
During one cycle is achieved, the input/output timing apply the same manner as the former cycle.
t
OH
t
OH
t
AA
t
CAC
t
CAC
t
AA
t
OEA
t
DZO
t
ON
t
RAC
t
RCD
t
OFR
t
RCS
t
RCH
t
WPZ
t
RCS
t
RCH
t
CAL
t
WEZ
t
ON
t
WPZ
t
ON
t
WEZ
t
WPZ
t
CDD
t
WED
t
WEZ
t
ON
t
AR
t
ASC
t
RDD
HIGH-Z
HIGH-Z
t
RAD
COL
ADD
t
CAC
相關(guān)PDF資料
PDF描述
MB8116165A-70 CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級頁面存取模式動態(tài)RAM)
MB8116165B-50 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM)
MB8116165B-60 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM)
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MB8116400A-60 CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4 位快速頁面存取模式動態(tài)RAM)
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