參數(shù)資料
型號(hào)： MB8116165A-60
廠商： Fujitsu Limited
英文描述： CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 100萬(wàn)× 16位的超頁(yè)模式動(dòng)態(tài)RAM的CMOS（100萬(wàn)× 16位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 27/30頁(yè)
文件大?。?/td> 376K
代理商： MB8116165A-60
27
MB8116165A-60/MB8116165A-70
LCAS
or
UCAS
Fig. 20 – SELF REFRESH CYCLE (A
0
- A
11
= WE = OE = “H” or “L”)
(At recommended operating conditions unless otherwise noted.)
Note: Assumes self refresh cycle only
Parameter
Unit
Min.
Max.
No.
Min.
Max.
74
—
100
100
Symbol
75
124
—
—
104
76
–50
–50
—
—
—
μ
s
ns
ns
RAS Pulse Width
RAS Precharge Time
CAS Hold Time
MB81V16165A-70
MB81V16165A-70
t
RASS
t
RPS
t
CHS
DESCRIPTION
The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip
is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter
and timing generator.
If CAS goes to “L” before RAS goes to “L” (CBR) and the condition of CAS “L” and RAS “L” is kept for term of t
RASS
(more than 100
μ
s), the device can enter the self refresh cycle. Following that, refresh operation is automatically executed at fixed intervals using
internal refresh address counter during “RAS=L” and “CAS=L”.
Exit from self refresh cycle is performed by toggling of /RAS and /CAS to “H” with specified t
CHS
min.. In this time, RAS must be
kept “H” with specified t
RPS
min.
Using self refresh mode, data can be retained without external CAS signal during system is in standby.
Restruction for Self refresh operation ;
For self refresh operation, the notice below must be considered.
1) In the case that distributed CBR refresh are operated between read/write cycles
Self refresh cycles can be executed without special rule if 4,096 cycles of distributed CBR refresh are executed within
t
REF
max.
2) In the case that burst CBR refresh or distributed/burst/RAS-only refresh are operated between read/write cycles
4,096 times of burst CBR refresh or 4,096 times of burst/RAS-only refresh must be executed before and after Self refresh
cycles.
V
IH
V
IL
RAS
“H” or “L”
V
IH
V
IL
RAS
V
IH
V
IL
V
OH
V
OL
DQ
(Output)
t
NS
< 4 ms
4,096 burst refresh cycle
Read/Write operation
4,096 burst refresh cycle
Self Refresh operation
t
RASS
Read/Write operation
t
SN
< 4 ms
A
0
to A
11
, WE, OE = “H” or “L”
HIGH-Z
t
RASS
t
RPS
t
RPC
t
CHS
t
CSR
t
CPN
t
OFF
t
OH
* read/write operation can be performed non refresh time within t
NS
or t
SN
相關(guān)PDF資料
PDF描述
MB8116165A-70 CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8116165B-50 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8116165B-60 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8116400A-50 CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8116400A-60 CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
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