參數(shù)資料
型號(hào): MB81V17805B-50
廠商: Fujitsu Limited
英文描述: 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述: 200萬(wàn)× 8位超頁(yè)模式動(dòng)態(tài)RAM的CMOS(200萬(wàn)× 8位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存)
文件頁(yè)數(shù): 20/29頁(yè)
文件大?。?/td> 557K
代理商: MB81V17805B-50
20
MB81V17805B-50/-60
t
RASP
t
RP
ROW
ADD
t
RSH
t
CAS
t
HPC
t
RCD
t
CSH
t
CAS
t
ASC
t
CAH
COL
ADD
COL
ADD
HIGH-Z
t
CAS
t
CP
COL
ADD
t
CAH
t
RAL
t
ASC
t
CAH
VALID
DATA
VALID
DATA
VALID
DATA
t
WCS
t
WCH
t
WCS
t
WCH
t
WCS
t
WCH
t
DS
t
DH
t
ASC
t
DS
t
DH
t
DS
t
DH
t
AR
t
WCR
t
DHR
t
RHCP
During one cycle is achieved, the input/output timing apply the same manner as the former cycle.
t
CWL
t
CWL
t
RWL
DESCRIPTION
The hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except the states of
WE and OE are reversed. Data appearing on the DQ pins are latched on the falling edge of CAS and the data is written into the
memory. During the hyper page mode early write cycle, including the delayed (OE) write and read-modify-write cycles, t
CWL
must
be satisfied.
Fig. 12 – HYPER PAGE MODE EARLY WRITE CYCLE
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H
L” or “L
H” transition (Address and DQ)
A
0
to A
10
V
IH
V
IL
RAS
V
IH
V
IL
CAS
V
IH
V
IL
WE
V
IH
V
IL
DQ
(Output)
V
OH
V
OL
DQ
(Input)
V
IH
V
IL
t
ASR
t
RAH
t
CRP
t
CWL
相關(guān)PDF資料
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