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參數(shù)資料
| 型號： | MB81V18160A-70L |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 1M ×16 BIT Fast Page Mode Dynamic RAM(CMOS 1M ×16 位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 100萬× 16位快速頁面模式動態(tài)RAM的CMOS（100萬× 16位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 19/25頁 |
| 文件大小： | 579K |
| 代理商： | MB81V18160A-70L |
19
MB81V18160A-60/60L/-70/70L
DESCRIPTION
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If LCAS or UCAS is
held Low for the specified setup time (t
CSR
) before RAS goes Low, the on-chip refresh control clock generators and refresh address
counter are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented in
preparation for the next CAS-before-RAS refresh operation.
Fig. 13 – RAS-ONLY REFRESH (WE = OE = “H” or “L”)
Fig. 14 – CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = “H” or “L”)
DESCRIPTION
Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 1,024 row addresses
every 16.4-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden refresh.
RAS-only refresh is performed by keeping RAS Low and LCAS and UCAS High throughout the cycle; the row address to be refreshed
is latched on the falling edge of RAS. During RAS-only refresh, DQ pins are kept in a high-impedance state.
RAS
V
IH
V
IL
V
IH
V
IL
A
0
to A
9
V
OH
V
OL
V
IH
V
IL
t
RC
DQ
(Output)
t
RP
t
ASR
t
RPC
HIGH-Z
t
RAH
t
OH
t
CRP
t
RAS
t
OFF
ROW ADDRESS
LCAS
or
UCAS
t
CRP
RAS
V
IH
V
IL
t
RC
DQ
(Output)
HIGH-Z
t
RAS
V
IH
V
IL
t
RPC
t
CPN
t
CSR
t
CHR
t
RP
t
OFF
t
OH
LCAS
or
UCAS
V
OH
V
OL
t
CPN
t
CSR
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
→
“L” or “L”
→
“H” transition (Address and DQ)
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
→
“L” or “L”
→
“H” transition (Address and DQ)
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