參數(shù)資料
型號(hào)： MB81V4260S-60
廠商： Fujitsu Limited
英文描述： CMOS 256K ×16 BIT FAST PAGE MODE DYNAMIC RAM(CMOS 256K ×16 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 256K × 16位快速頁(yè)面模式的動(dòng)態(tài)隨機(jī)存儲(chǔ)器（的CMOS 256K × 16位快速頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 23/28頁(yè)
文件大小： 360K
代理商： MB81V4260S-60
23
MB81V4260S-60/MB81V4260S-70
Fig. 16 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
(At recommended operating conditions unless otherwise noted.)
Note: Assumes that CAS-before-RAS refresh counter test cycle only.
V
IH
V
IL
V
IH
V
IL
RAS
A
0
to A
8
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
WE
DQ
(Input)
OE
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the
functionality of CAS-before-RAS refresh circuitry. After a CAS-before-RAS refresh cycle, if LCAS or UCAS makes a transition from
High to Low while RAS is held Low, read and write operations are enabled as shown above. Row and column addresses are
defined as follows:
Row Address: Bits A
0
through A
8
are defined by the on-chip refresh counter.
Column Address: Bits A
0
through A
8
are defined by latching levels on A
0
-A
8
at the second falling edge of LCAS or UCAS.
The CAS-before-RAS Counter Test procedure is as follows ;
1) Normalize the internal refresh address counter by using 8 RAS only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 512 row addresses at the same column address by using CBR refresh counter test cycles.
4) Read “0” written in procedure 3) by using normal read cycle and check; After reading “0” and check are completed
(or simultaneously), write “1” to the same addresses by using normal write cycle (or read-modify-write cycle).
5) Read and check data “1” written in procedure 4) by using CBR refresh counter test cycle for all 512 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
DQ
(Output)
CAS to WE Delay Time
Parameter
Unit
Min.
Max.
ns
No.
Min.
Max.
90
—
55
55
Symbol
91
30
—
—
ns
30
Column Address Hold Time
92
CAS Pulse width
93
RAS Hold Time
80
—
—
ns
80
55
—
—
ns
55
94
55
—
—
ns
55
—
—
ns
85
—
85
CAS Hold Time
95
MB81V4260S-60
MB81V4260S-70
Access Time from CAS
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FCSH
t
FRSH
LCAS
or
UCAS
t
ON
t
OEA
t
FCWD
“H” or “L”
Valid Data
HIGH-Z
HIGH-Z
t
OEH
HIGH-Z
VALID DATA IN
COLUMN ADDRESS
t
RP
t
FRSH
t
FCAS
t
FCSH
t
CHR
t
CSR
t
CP
t
ASC
t
RAL
t
AR
t
FCAH
t
RCS
t
RWL
t
WCR
t
DH
t
WP
t
DS
t
DZC
t
OED
t
FCAC
t
DZO
t
OEZ
t
DHR
t
CWL
t
CDD
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