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| 型號： | MB81V4260S-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 256K ×16 BIT FAST PAGE MODE DYNAMIC RAM(CMOS 256K ×16 位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 256K × 16位快速頁面模式的動態(tài)隨機(jī)存儲器（的CMOS 256K × 16位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 24/28頁 |
| 文件大小： | 360K |
| 代理商： | MB81V4260S-60 |
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MB81V4260S-60/MB81V4260S-70
DQ
(Output)
CAS
Fig. 17 – SELF REFRESH CYCLE (A
0
- A
9
= WE = OE = “H” or “L”)
(At recommended operating conditions unless otherwise noted.)
Note: Assumes Self refresh cycles only.
Parameter
Unit
Min.
Max.
No.
Min.
Max.
100
—
100
100
Symbol
101
125
—
—
110
102
–50
–50
—
—
—
ns
ns
ns
RAS Pulse Width
RAS Precharge Time
CAS Hold Time
MB81V4260S-60
MB81V4260S-70
t
RASS
t
RPS
t
CHS
“H” or “L”
V
IH
V
IL
RAS
V
IH
V
IL
V
OH
V
OL
t
CHS
t
OFF
DESCRIPTION
The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip
is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter.
If CAS goes to “L” before RAS goes to “L” (CBR) and the condition of CAS “L” and RAS “L” is kept for term of tRASS (more than
100
μ
s), the device can be entered the self refresh cycle. And after that, refresh operation is automatically executed per fixed interval
using internal refresh address counter during “RAS=L” and “CAS=L”.
And exit from self refresh cycle is performed by toggling of RAS and CAS to “H” with specifying t
CHS
min.
Restruction for Self refresh operation ;
For self refresh operation, the notice below must be considered.
1) In the case that distribut CBR refresh are operated in read/write cycles
Self refresh cycles can be executed without special rule if 512 cycles of distribut CBR refresh are executed within t
REF
max..
2) In the case that burst CBR refresh or RAS only refresh are operated in read/write cycles
512 times of burst CBR refresh or 512 times of burst RAS only refresh must be executed before and after Self refresh
cycles.
512 times of burst refresh
512 times of burst refresh
Read/Write operation
Self Refresh operation
t
RASS
Read/Write operation
V
IH
V
IL
RAS
t
NS
< 0.5 ms
t
SN
< 0.5 ms
HIGH-Z
t
RPC
t
RPS
t
RASS
t
CSR
t
OH
t
CPN
相關(guān)PDF資料 |
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| MB81V4260S-70 | CMOS 256K ×16 BIT FAST PAGE MODE DYNAMIC RAM(CMOS 256K ×16 位快速頁面存取模式動態(tài)RAM) |
| MB81V4265-60 | CMOS 256K ×16BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級頁面存取模式動態(tài)RAM) |
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| MB81V4265S-60 | CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16位超級頁面存取模式動態(tài)RAM) |
| MB81V4265S-60L | CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級頁面存取模式動態(tài)RAM) |
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