參數(shù)資料
型號(hào): MB81V4265-60
廠商: Fujitsu Limited
英文描述: CMOS 256K ×16BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述: 256K × 16位的CMOS超頁(yè)模式動(dòng)態(tài)RAM的CMOS(256K × 16位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存)
文件頁(yè)數(shù): 1/27頁(yè)
文件大?。?/td> 366K
代理商: MB81V4265-60
DS05-10197-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
256K
HYPER PAGE MODE DYNAMIC RAM
×
16 BITS
MB81V4265-60/-70
CMOS 262,144
×
16 BITS Hyper Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB81V4265 is a fully decoded CMOS Dynamic RAM (DRAM) that contains 4,194,304 memory cells
accessible in 16-bit increments. The MB81V4265 features the “hyper page” mode of operation which provides
extended valid time for data output and higher speed random access of up to 512
row than the fast page mode. The MB81V4265-60/-70 DRAMs are ideally suited for memory applications such
as embedded control, buffer, portable computers, and video imaging equipment where very low power dissipation
and high bandwidth are basic requirements of the design.
The MB81V4265 is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon process.
This process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft
errors and extends the time interval between memory refreshes.
×
16-bits of data within the same
I
PRODUCT LINE & FEATURES
Parameter
MB81V4265-60
60 ns max.
20 ns max.
30 ns max.
104 ns min.
25 ns min.
378 mW max.
7.2 mW max. (LVTTL level)/3.6 mW max. (CMOS level)
MB81V4265-70
70 ns max.
20 ns max.
35 ns max.
119 ns min.
30 ns min.
335 mW max.
RAS Access Time
CAS Access Time
Address Access Time
Random Cycle Time
Hyper Page Mode Cycle Time
Low Power Dissipation
Operating current
Standby current
262,144 words
×
16 bits organization
Silicon gate, CMOS, Advanced Stacked
Capacitor Cell
All input and output are LVTTL compatible
512 refresh cycles every 8.2 ms
9 rows
×
9 columns, addressing scheme
Early write or OE controlled Write capability
RAS-only, CAS-before-RAS, or Hidden Refresh
Hyper page mode, Read-Modify-Write capability
On chip substrate bias generator for high
performance
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
相關(guān)PDF資料
PDF描述
MB81V4265-70 CMOS 256K ×16BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB81V4265S-60 CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB81V4265S-60L CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB81V4265S-70L CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB81V4265S-70 CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
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