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參數(shù)資料
| 型號： | MB81V4265-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 256K ×16BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 256K × 16位的CMOS超頁模式動態(tài)RAM的CMOS（256K × 16位超級頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 5/27頁 |
| 文件大?。?/td> | 366K |
| 代理商： | MB81V4265-60 |
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5
MB81V4265-60/-70
I
RECOMMENDED OPERATING CONDITIONS
* :Undershoots of up to –2.0 volts with a pulse width not exceeding 20 ns are acceptable.
I
FUNCTIONAL OPERATION
ADDRESS INPUTS
Eighteen input bits are required to decode any sixteen of 4,194,304 cell addresses in the memory matrix. Since
only nine address bits (A0 to A8) are available, the column and row inputs are separately strobed by LCAS or
UCAS and RAS as shown in Figure 1. First, nine row address bits are input on pins A0-through-A9 and latched
with the row address strobe (RAS) then, nine column address bits are input and latched with the column address
strobe (LCAS or UCAS). Both row and column addresses must be stable on or before the falling edges of RAS
and LCAS or UCAS, respectively. The address latches are of the flow-through type; thus, address information
appearing after t
RAH
(min) + t
T
is automatically treated as the column address.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of three basic ways : an early write cycle, an OE (delayed) write cycle,
and a read-modify-write cycle. The falling edge of WE or LCAS / UCAS, whichever is later, serves as the input
data-latch strobe. In an early write cycle, the input data of DQ
1
to DQ
8
is strobed by LCAS and DQ
9
to DQ
16
is
strobed by UCAS and the setup/hold times are referenced to each LCAS and UCAS because WE goes Low
before LCAS / UCAS. In a delayed write or a read-modify-write cycle, WE goes Low after LCAS / UCAS; thus,
input data is strobed by WE and all setup/hold times are referenced to the write-enable signal.
DATA OUTPUT
The three-state buffers are LVTTL compatible with a fanout of one TTL load. Polarity of the output data is identical
to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes
Low. When a read or read-modify-write cycle is executed, valid outputs and High-Z state are obtained under
the following conditions:
t
RAC
:
from the falling edge of RAS when t
RCD
(max) is satisfied.
t
CAC
:
from the falling edge of LCAS (for DQ
1
to DQ
8
) UCAS (for DQ
9
to DQ
16
) when t
RCD
is greater than
t
RCD
(max).
t
AA
:
from column address input when t
RAD
is greater than t
RAD
(max), and t
RCD
(max) is satisfied.
t
OEA
:
from the falling edge of OE when OE is brought Low after t
RAC
, t
CAC
, or t
AA
.
t
OEZ
:
from OE inactive
t
OFF
:
from CAS inactive while RAS inactive.
t
OFR
:
from RAS inactive while CAS inactive.
t
WEZ
:
from WE active while CAS inactive.
The data remains valid after either OE is inactive, or both RAS and LCAS (and/or UCAS) are inactive, or CAS
is reactived. When an early write is executed, the output buffers remain in a high-impedance state during the
entire cycle.
Parameter
Notes
Symbol
Min.
Typ.
Max.
Unit
Ambient
Operating Temp.
Supply Voltage
*1
V
CC
V
SS
V
IH
V
IL
3.0
0
2.0
–0.3
3.3
0
—
—
3.6
0
V
0
°
C to +70
°
C
Input High Voltage, all inputs
Input Low Voltage, all inputs*
*1
*1
V
CC
+0.3
0.8
V
V
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